{"@ID": "1209", "@Name": "Failure to Disable Reserved Bits", "@Abstraction": "Base", "@Structure": "Simple", "@Status": "Incomplete", "Description": "The reserved bits in a hardware design are not disabled prior to production.", "Related_Weaknesses": {"Related_Weakness": {"@Nature": "ChildOf", "@CWE_ID": "710", "@View_ID": "1000", "@Ordinal": "Primary"}}, "Weakness_Ordinalities": {"Weakness_Ordinality": {"Ordinality": "Primary"}}, "Applicable_Platforms": {"Language": {"@Class": "Not Language-Specific", "@Prevalence": "Undetermined"}, "Operating_System": {"@Class": "Not OS-Specific", "@Prevalence": "Undetermined"}, "Architecture": {"@Class": "Not Architecture-Specific", "@Prevalence": "Undetermined"}, "Technology": {"@Class": "System on Chip", "@Prevalence": "Undetermined"}}, "Background_Details": {"Background_Detail": "Reserved bits are labeled as such so they can be\n\t\tallocated for a later purpose. Typically, reserved\n\t\tbits are used for future capabilities and should not\n\t\tsupport any functional logic in the design.  They are\n\t\tnot supposed to do anything in the current design."}, "Modes_Of_Introduction": {"Introduction": [{"Phase": ["Architecture and Design", "Implementation"], "Note": "The Designer and Implementer have to make a\n                    conscious choice to do this. Designers might\n                    covertly use reserved bits to debug or further\n                    develop new capabilities in production\n                    hardware. Designers might want to use these bits\n                    to debug or control/configure a future capability\n                    to help minimize time to market (TTM)."}, {"Phase": "Documentation", "Note": "If documentation labels anything \"for future use\", \"reserved\", or the like, such labeling could indicate to an attacker a potential attack point."}]}, "Common_Consequences": {"Consequence": {"Scope": ["Confidentiality", "Integrity", "Availability", "Access Control", "Accountability", "Authentication", "Authorization", "Non-Repudiation"], "Impact": "Varies by Context", "Note": "If the logic being controlled by these bits\n                    is still enabled in production, an adversary could\n                    use the logic to induce unwanted/unsupported\n                    behavior in the hardware. Adversaries with access\n                    to these bits will write to them in hopes of\n                    compromising hardware state. This type of weakness\n                    all depends on the capabilities of the logic being\n                    controlled or configured by the reserved\n                    bits."}}, "Potential_Mitigations": {"Mitigation": [{"Phase": ["Architecture and Design", "Implementation"], "Description": {"xhtml:p": "Include a feature to disable reserved bits.", "#text_blocks": ["Include a feature to disable reserved bits."]}}, {"Phase": "Integration", "Description": {"xhtml:p": "Any writes to these reserve bits are blocked (e.g., ignored, access-protected, etc.), or an exception can be asserted.", "#text_blocks": ["Any writes to these reserve bits are blocked (e.g., ignored, access-protected, etc.), or an exception can be asserted."]}}]}, "Demonstrative_Examples": {"Demonstrative_Example": {"Intro_Text": "Assume a hardware Intellectual Property (IP) has address space 0x0-0x0F for its configuration registers, with the last one labeled reserved (i.e. 0x0F).  Therefore inside the Finite State Machine (FSM), the code is as follows:", "Example_Code": [{"@Nature": "Bad", "@Language": "Verilog", "xhtml:br": [null, null, null], "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": null, "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": [null, null], "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": null, "#text": "gpio_out = 1;"}, "#text": "begin\n\t\t\t  \n\t\t\t  end"}, "#text": "4'b1111 : //0x0F"}, "#text": "reg gpio_out = 0;  //gpio should remain low for normal operation\n                      \n                      case (register_address)", "#text_blocks": ["reg gpio_out = 0;  //gpio should remain low for normal operation", "case (register_address)", "4'b1111 : //0x0F", "begin", "gpio_out = 1;", "end"]}, {"@Nature": "Good", "@Language": "Verilog", "xhtml:br": [null, null, null], "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": [null, null], "#text": "//4'b1111 : //0x0F\n                  \t    default: gpio_out = gpio_out;"}, "#text": "reg gpio_out = 0;  //gpio should remain low for normal operation\n\t\t\t  \n                  \t  case (register_address)", "#text_blocks": ["reg gpio_out = 0;  //gpio should remain low for normal operation", "case (register_address)", "//4'b1111 : //0x0F", "default: gpio_out = gpio_out;"]}], "Body_Text": {"xhtml:p": ["An adversary may perform writes to reserved address space in hopes of changing the behavior of the hardware. In the code above, the GPIO pin should remain low for normal operation.  However, it can be asserted by accessing the reserved address space (0x0F).  This may be a concern if the GPIO state is being used as an indicator of health (e.g. if asserted the hardware may respond by shutting down or resetting the system, which may not be the correct action the system should perform).", "In the code below, the condition \"register_address = 0X0F\" is commented out, and a default is provided that will catch any values of register_address not explicitly accounted for and take no action with regards to gpio_out. This means that an attacker who is able to write 0X0F to register_address will not enable any undocumented \"features\" in the process."], "#text_blocks": ["An adversary may perform writes to reserved address space in hopes of changing the behavior of the hardware. In the code above, the GPIO pin should remain low for normal operation.  However, it can be asserted by accessing the reserved address space (0x0F).  This may be a concern if the GPIO state is being used as an indicator of health (e.g. if asserted the hardware may respond by shutting down or resetting the system, which may not be the correct action the system should perform).", "In the code below, the condition \"register_address = 0X0F\" is commented out, and a default is provided that will catch any values of register_address not explicitly accounted for and take no action with regards to gpio_out. This means that an attacker who is able to write 0X0F to register_address will not enable any undocumented \"features\" in the process."]}}}, "Related_Attack_Patterns": {"Related_Attack_Pattern": {"@CAPEC_ID": "121"}}, "Mapping_Notes": {"Usage": "Allowed", "Rationale": "This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.", "Comments": "Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.", "Reasons": {"Reason": {"@Type": "Acceptable-Use"}}}, "Content_History": {"Submission": {"Submission_Name": "Brent Sherman", "Submission_Organization": "Intel Corporation", "Submission_Date": "2020-02-06", "Submission_Version": "4.0", "Submission_ReleaseDate": "2020-02-24"}, "Modification": [{"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2020-08-20", "Modification_Version": "4.2", "Modification_ReleaseDate": "2020-08-20", "Modification_Comment": "updated Related_Attack_Patterns"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2021-10-28", "Modification_Version": "4.6", "Modification_ReleaseDate": "2021-10-28", "Modification_Comment": "updated Potential_Mitigations"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2022-10-13", "Modification_Version": "4.9", "Modification_ReleaseDate": "2022-10-13", "Modification_Comment": "updated Demonstrative_Examples"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2023-01-31", "Modification_Version": "4.10", "Modification_ReleaseDate": "2023-01-31", "Modification_Comment": "updated Demonstrative_Examples"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2023-04-27", "Modification_Version": "4.11", "Modification_ReleaseDate": "2023-04-27", "Modification_Comment": "updated Relationships"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2023-06-29", "Modification_Version": "4.12", "Modification_ReleaseDate": "2023-06-29", "Modification_Comment": "updated Mapping_Notes"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2025-12-11", "Modification_Version": "4.19", "Modification_ReleaseDate": "2025-12-11", "Modification_Comment": "updated Weakness_Ordinalities"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2026-10-28", "Modification_Version": "5.0", "Modification_ReleaseDate": "2026-10-28", "Modification_Comment": "updated Background_Details, Common_Consequences, Description, Modes_of_Introduction, Time_of_Introduction"}]}, "entry_type": "Weakness"}