{"@ID": "1221", "@Name": "Incorrect Register Defaults or Module Parameters", "@Abstraction": "Base", "@Structure": "Simple", "@Status": "Incomplete", "Description": "Hardware description language code incorrectly defines register defaults or hardware Intellectual Property (IP) parameters to insecure values.", "Extended_Description": {"xhtml:p": ["Integrated circuits and hardware IP software programmable controls and settings are commonly stored in register circuits. These register contents have to be initialized at hardware reset to defined default values that are hard coded in the hardware description language (HDL) code of the hardware unit. Hardware descriptive languages also support definition of parameter variables, which can be defined in code during instantiation of the hardware IP module. Such parameters are generally used to configure a specific instance of a hardware IP in the design.", "The system security settings of a hardware design can be affected by incorrectly defined default values or IP parameters. The hardware IP would be in an insecure state at power reset, and this can be exposed or exploited by untrusted software running on the system. Both register defaults and parameters are hardcoded values, which cannot be changed using software or firmware patches but must be changed in hardware silicon. Thus, such security issues are considerably more difficult to address later in the lifecycle. Hardware designs can have a large number of such parameters and register defaults settings, and it is important to have design tool support to check these settings in an automated way and be able to identify which settings are security sensitive."]}, "Related_Weaknesses": {"Related_Weakness": {"@Nature": "ChildOf", "@CWE_ID": "1419", "@View_ID": "1000", "@Ordinal": "Primary"}}, "Weakness_Ordinalities": {"Weakness_Ordinality": {"Ordinality": "Primary"}}, "Applicable_Platforms": {"Language": [{"@Name": "Verilog", "@Prevalence": "Undetermined"}, {"@Name": "VHDL", "@Prevalence": "Undetermined"}], "Technology": {"@Class": "Not Technology-Specific", "@Prevalence": "Undetermined"}}, "Modes_Of_Introduction": {"Introduction": {"Phase": "Implementation", "Note": "Such issues could be introduced during implementation of hardware design, since IP parameters and defaults are defined in HDL code and identified later during Testing or System Configuration phases."}}, "Common_Consequences": {"Consequence": {"Scope": ["Confidentiality", "Integrity", "Availability", "Access Control"], "Impact": "Varies by Context", "Note": "Degradation of system functionality, or loss of access control enforcement can occur."}}, "Detection_Methods": {"Detection_Method": {"Method": "Automated Analysis", "Description": "Use automated tools to test that values are configured per design specifications."}}, "Potential_Mitigations": {"Mitigation": [{"Phase": "Architecture and Design", "Description": "During hardware design, all the system parameters and register defaults must be reviewed to identify security sensitive settings."}, {"Phase": "Implementation", "Description": "The default values of these security sensitive settings need to be defined as part of the design review phase."}]}, "Demonstrative_Examples": {"Demonstrative_Example": [{"@Demonstrative_Example_ID": "DX-162", "Intro_Text": "Consider example design module system verilog code shown below. The register_example module is an example parameterized module that defines two parameters, REGISTER_WIDTH and REGISTER_DEFAULT. Register_example module defines a Secure_mode setting, which when set makes the register content read-only and not modifiable by software writes. register_top module instantiates two registers, Insecure_Device_ID_1 and Insecure_Device_ID_2. Generally, registers containing device identifier values are required to be read only to prevent any possibility of software modifying these values.", "Example_Code": [{"@Nature": "Bad", "@Language": "Verilog", "xhtml:br": [null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null], "xhtml:div": [{"@style": "margin-left:1em;", "xhtml:br": [null, null, null, null, null, null], "xhtml:div": [{"@style": "margin-left:1em;", "xhtml:br": [null, null], "#text": "Data_out <= REGISTER_DEFAULT; // Register content set to Default at reset \n\t\t\t    Secure_mode <= REGISTER_DEFAULT[0]; // Register Secure_mode set at reset"}, {"@style": "margin-left:1em;", "xhtml:br": null, "#text": "Data_out <= Data_in;"}], "#text": "if (~resetn) \n\t\t\t  begin \n\t\t\t  \n\t\t\t  end \n\t\t\t  else if (write & ~Secure_mode) \n\t\t\t  begin \n\t\t\t  \n\t\t\t  end"}, {"@style": "margin-left:1em;", "xhtml:br": [null, null], "#text": ".REGISTER_WIDTH (32), \n\t\t\t  .REGISTER_DEFAULT (1224) // Incorrect Default value used bit 0 is 0."}, {"@style": "margin-left:1em;", "xhtml:br": [null, null, null, null, null], "#text": ".Data_in (Data_in), \n\t\t\t  .Data_out (Secure_reg), \n\t\t\t  .Clk (Clk), \n\t\t\t  .resetn (resetn), \n\t\t\t  .write (write)"}, {"@style": "margin-left:1em;", "xhtml:br": null, "#text": ".REGISTER_WIDTH (32) // Default not defined 2^32-2 value will be used as default."}, {"@style": "margin-left:1em;", "xhtml:br": [null, null, null, null, null], "#text": ".Data_in (Data_in), \n\t\t\t  .Data_out (Insecure_reg), \n\t\t\t  .Clk (Clk), \n\t\t\t  .resetn (resetn), \n\t\t\t  .write (write)"}], "#text": "// Parameterized Register module example \n\t\t\t// Secure_mode : REGISTER_DEFAULT[0] : When set to 1 register is read only and not writable// \n\t\t\tmodule register_example \n\t\t\t#( \n\t\t\tparameter REGISTER_WIDTH = 8, // Parameter defines width of register, default 8 bits \n\t\t\tparameter [REGISTER_WIDTH-1:0] REGISTER_DEFAULT = 2**REGISTER_WIDTH -2 // Default value of register computed from Width. Sets all bits to 1s except bit 0 (Secure _mode) \n\t\t\t) \n\t\t\t( \n\t\t\tinput [REGISTER_WIDTH-1:0] Data_in, \n\t\t\tinput Clk, \n\t\t\tinput resetn, \n\t\t\tinput write, \n\t\t\toutput reg [REGISTER_WIDTH-1:0] Data_out \n\t\t\t); \n\t\t\t\n\t\t\treg Secure_mode; \n\t\t\t\n\t\t\talways @(posedge Clk or negedge resetn) \n\t\t\t\n\t\t\tendmodule \n                        \n                        \n\t\t\tmodule register_top \n\t\t\t( \n\t\t\tinput Clk, \n\t\t\tinput resetn, \n\t\t\tinput write, \n\t\t\tinput [31:0] Data_in, \n\t\t\toutput reg [31:0] Secure_reg, \n\t\t\toutput reg [31:0] Insecure_reg \n\t\t\t); \n\t\t\t\n\t\t\tregister_example #( \n\t\t\t\n\t\t\t) Insecure_Device_ID_1 ( \n\t\t\t\n\t\t\t); \n                        \n\t\t\tregister_example #(\n\t\t\t\n\t\t\t) Insecure_Device_ID_2 ( \n\t\t\t\n\t\t\t); \n                        \n\t\t\tendmodule"}, {"@Nature": "Good", "@Language": "Verilog", "xhtml:br": [null, null], "xhtml:div": [{"@style": "margin-left:1em;", "xhtml:br": [null, null], "#text": ".REGISTER_WIDTH (32), \n\t\t\t.REGISTER_DEFAULT (1225) // Correct default value set, to enable Secure_mode"}, {"@style": "margin-left:1em;", "xhtml:br": [null, null, null, null, null], "#text": ".Data_in (Data_in), \n\t\t\t.Data_out (Secure_reg), \n\t\t\t.Clk (Clk), \n\t\t\t.resetn (resetn), \n\t\t\t.write (write)"}], "#text": "register_example #( \n\t\t      \n\t\t      ) Secure_Device_ID_example ( \n\t\t      \n\t\t      );"}], "Body_Text": ["These example instantiations show how, in a hardware design, it would be possible to instantiate the register module with insecure defaults and parameters.", "In the example design, both registers will be software writable since Secure_mode is defined as zero."]}, {"Intro_Text": "The example code is taken from the fuse memory inside the buggy OpenPiton SoC of HACK@DAC'21 [REF-1356]. Fuse memory can be used to store key hashes, password hashes, and configuration information. For example, the password hashes of JTAG and HMAC are stored in the fuse memory in the OpenPiton design.", "Body_Text": ["During the firmware setup phase, data in the Fuse memory are transferred into the registers of the corresponding SoC peripherals for initialization. However, if the offset to access the password hash is set incorrectly, programs cannot access the correct password hash from the fuse memory, breaking the functionalities of the peripherals and even exposing sensitive information through other peripherals.", "The following vulnerable code accesses the JTAG password hash from the fuse memory. However, the JTAG_OFFSET is incorrect, and the fuse memory outputs the wrong values to jtag_hash_o. Moreover, setting incorrect offset gives the ability to attackers to access JTAG by knowing other low-privileged peripherals' passwords.", {"xhtml:br": null, "#text": "To mitigate this, change JTAG_OFFSET to the correct address of the JTAG key [REF-1357]."}], "Example_Code": [{"@Nature": "Bad", "@Language": "Verilog", "xhtml:b": ["parameter  MEM_SIZE = 100;", "localparam JTAG_OFFSET = 81;"], "xhtml:br": [null, null, null, null, null, null, null, null], "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": [null, null, null], "#text": "// JTAG expected hamc hash\n\t\t\t\t\t\t32'h49ac13af, 32'h1276f1b8, 32'h6703193a, 32'h65eb531b,\n\t\t\t\t\t\t32'h3025ccca, 32'h3e8861f4, 32'h329edfe5, 32'h98f763b4,"}, "#text": "const logic [MEM_SIZE-1:0][31:0] mem = {\n\t\t\t\t\t\n\t\t\t\t\t...\n\t\t\t\t\tassign jtag_hash_o = {mem[JTAG_OFFSET-1],mem[JTAG_OFFSET-2],mem[JTAG_OFFSET-3],\n\t\t\t\t\tmem[JTAG_OFFSET-4],mem[JTAG_OFFSET-5],mem[JTAG_OFFSET-6],mem[JTAG_OFFSET-7],mem[JTAG_OFFSET-8]};\n\t\t\t\t\t..."}, {"@Nature": "Good", "@Language": "Verilog", "xhtml:br": [null, null], "xhtml:b": "localparam JTAG_OFFSET = 100;", "#text": "parameter  MEM_SIZE = 100;"}]}, {"@Demonstrative_Example_ID": "DX-222", "Intro_Text": "The following example code is excerpted from the Access Control module, acct_wrapper, in the Hack@DAC'21 buggy OpenPiton System-on-Chip (SoC). Within this module, a set of memory-mapped I/O registers, referred to as acct_mem, each 32-bit wide, is utilized to store access control permissions for peripherals [REF-1437]. Access control registers are typically used to define and enforce permissions and access rights for various system resources.", "Body_Text": ["However, in the buggy SoC, these registers are all enabled at reset, i.e., essentially granting unrestricted access to all system resources [REF-1438]. This will introduce security vulnerabilities and risks to the system, such as privilege escalation or exposing sensitive information to unauthorized users or processes.", "To fix this issue, the access control registers must be properly initialized during the reset phase of the SoC. Correct initialization values should be established to maintain the system's integrity, security, predictable behavior, and allow proper control of peripherals. The specifics of what values should be set depend on the SoC's design and the requirements of the system. To address the problem depicted in the bad code example [REF-1438], the default value for \"acct_mem\" should be set to 32'h00000000 (see good code example [REF-1439]). This ensures that during startup or after any reset, access to protected data is restricted until the system setup is complete and security procedures properly configure the access control settings."], "Example_Code": [{"@Nature": "Bad", "@Language": "Verilog", "xhtml:br": [null, null], "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": null, "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": [null, null], "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": null, "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": [null, null], "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": null, "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": [null, null], "xhtml:div": {"@style": "margin-left:1em;", "xhtml:b": "acct_mem[j] <= 32'hffffffff;", "xhtml:br": null}, "#text": "begin\n\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\tend"}, "#text": "for (j=0; j < AcCt_MEM_SIZE; j=j+1)"}, "#text": "begin\n\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\tend"}, "#text": "if(~(rst_ni && ~rst_6))"}, "#text": "begin\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t..."}, "#text": "always @(posedge clk_i)"}, "#text": "module acct_wrapper #(\n\t\t\t\t\t\t..."}, {"@Nature": "Good", "@Language": "Verilog", "xhtml:br": [null, null], "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": null, "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": [null, null], "xhtml:div": {"@style": "margin-left:1em;", "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": [null, null], "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": null, "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": [null, null], "xhtml:div": {"@style": "margin-left:1em;", "xhtml:b": "acct_mem[j] <= 32'h00000000;", "xhtml:br": null}, "#text": "begin\n\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\tend"}, "#text": "for (j=0; j < AcCt_MEM_SIZE; j=j+1)"}, "#text": "begin\n\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\tend"}, "#text": "if(~(rst_ni && ~rst_6))"}, "#text": "begin\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t..."}, "#text": "always @(posedge clk_i)"}, "#text": "module acct_wrapper #(\n\t\t\t\t\t\t..."}]}]}, "Related_Attack_Patterns": {"Related_Attack_Pattern": {"@CAPEC_ID": "166"}}, "References": {"Reference": [{"@External_Reference_ID": "REF-1356"}, {"@External_Reference_ID": "REF-1357"}, {"@External_Reference_ID": "REF-1437"}, {"@External_Reference_ID": "REF-1438"}, {"@External_Reference_ID": "REF-1439"}]}, "Mapping_Notes": {"Usage": "Allowed", "Rationale": "This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.", "Comments": "Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.", "Reasons": {"Reason": {"@Type": "Acceptable-Use"}}}, "Content_History": {"Submission": {"Submission_Name": "Arun Kanuparthi, Hareesh Khattri, Parbati Kumar Manna, Narasimha Kumar V Mangipudi", "Submission_Organization": "Intel Corporation", "Submission_Date": "2019-12-12", "Submission_Version": "4.0", "Submission_ReleaseDate": "2020-02-24"}, "Modification": [{"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2021-07-20", "Modification_Version": "4.5", "Modification_ReleaseDate": "2021-07-20", "Modification_Comment": "updated Related_Attack_Patterns"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2021-10-28", "Modification_Version": "4.6", "Modification_ReleaseDate": "2021-10-28", "Modification_Comment": "updated Common_Consequences"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2022-10-13", "Modification_Version": "4.9", "Modification_ReleaseDate": "2022-10-13", "Modification_Comment": "updated Demonstrative_Examples"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2023-04-27", "Modification_Version": "4.11", "Modification_ReleaseDate": "2023-04-27", "Modification_Comment": "updated Relationships"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2023-06-29", "Modification_Version": "4.12", "Modification_ReleaseDate": "2023-06-29", "Modification_Comment": "updated Mapping_Notes"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2023-10-26", "Modification_Version": "4.13", "Modification_ReleaseDate": "2023-10-26", "Modification_Comment": "updated Demonstrative_Examples, Description, References, Relationships"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2024-02-29", "Modification_Version": "4.14", "Modification_ReleaseDate": "2024-02-29", "Modification_Comment": "updated Demonstrative_Examples"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2024-07-16", "Modification_Version": "4.15", "Modification_ReleaseDate": "2024-07-16", "Modification_Comment": "updated Demonstrative_Examples, References"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2025-12-11", "Modification_Version": "4.19", "Modification_ReleaseDate": "2025-12-11", "Modification_Comment": "updated Detection_Factors, Potential_Mitigations, Weakness_Ordinalities"}], "Contribution": [{"@Type": "Content", "Contribution_Name": "Chen Chen, Rahul Kande, Jeyavijayan Rajendran", "Contribution_Organization": "Texas A&M University", "Contribution_Date": "2023-06-21", "Contribution_Comment": "suggested demonstrative example"}, {"@Type": "Content", "Contribution_Name": "Shaza Zeitouni, Mohamadreza Rostami, Ahmad-Reza Sadeghi", "Contribution_Organization": "Technical University of Darmstadt", "Contribution_Date": "2023-06-21", "Contribution_Comment": "suggested demonstrative example"}, {"@Type": "Content", "Contribution_Name": "Chen Chen, Rahul Kande, Jeyavijayan Rajendran", "Contribution_Organization": "Texas A&M University", "Contribution_Date": "2023-11-07", "Contribution_Comment": "suggested demonstrative example"}, {"@Type": "Content", "Contribution_Name": "Shaza Zeitouni, Mohamadreza Rostami, Ahmad-Reza Sadeghi", "Contribution_Organization": "Technical University of Darmstadt", "Contribution_Date": "2023-11-07", "Contribution_Comment": "suggested demonstrative example"}]}}