{"@ID": "1276", "@Name": "Hardware Child Block Incorrectly Connected to Parent System", "@Abstraction": "Base", "@Structure": "Simple", "@Status": "Incomplete", "Description": "Signals between a hardware IP and the parent system design are incorrectly connected causing security risks.", "Extended_Description": {"xhtml:p": "Individual hardware IP must communicate with the parent system in order for the product to function correctly and as intended. If implemented incorrectly, while not causing any apparent functional issues, may cause security issues. For example, if the IP should only be reset by a system-wide hard reset, but instead the reset input is connected to a software-triggered debug mode reset (which is also asserted during a hard reset), integrity of data inside the IP can be violated."}, "Related_Weaknesses": {"Related_Weakness": {"@Nature": "ChildOf", "@CWE_ID": "284", "@View_ID": "1000", "@Ordinal": "Primary"}}, "Weakness_Ordinalities": {"Weakness_Ordinality": {"Ordinality": "Primary"}}, "Applicable_Platforms": {"Language": {"@Class": "Not Language-Specific", "@Prevalence": "Undetermined"}, "Operating_System": {"@Class": "Not OS-Specific", "@Prevalence": "Undetermined"}, "Architecture": {"@Class": "Not Architecture-Specific", "@Prevalence": "Undetermined"}, "Technology": {"@Class": "Not Technology-Specific", "@Prevalence": "Undetermined"}}, "Modes_Of_Introduction": {"Introduction": {"Phase": "Implementation", "Note": "This weakness is introduced when integrating IP into a parent design."}}, "Common_Consequences": {"Consequence": {"Scope": ["Confidentiality", "Integrity", "Availability"], "Impact": "Varies by Context"}}, "Potential_Mitigations": {"Mitigation": {"Phase": "Testing", "Description": "System-level verification may be used to ensure that components are correctly connected and that design security requirements are not violated due to interactions between various IP blocks."}}, "Demonstrative_Examples": {"Demonstrative_Example": [{"Intro_Text": "Many SoCs use hardware to partition system resources between trusted and untrusted entities. One example of this concept is the Arm TrustZone, in which the processor and all security-aware IP attempt to isolate resources based on the status of a privilege bit. This privilege bit is part of the input interface in all TrustZone-aware IP. If this privilege bit is accidentally grounded or left unconnected when the IP is instantiated, privilege escalation of all input data may occur.", "Example_Code": [{"@Nature": "Bad", "@Language": "Verilog", "xhtml:br": [null, null, null, null, null, null], "xhtml:div": [{"@style": "margin-left:1em;", "xhtml:br": [null, null, null, null], "#text": "input clk, reset;\n\t\t\t\tinput [31:0] data_in;\n\t\t\t\tinput data_in_security_level;\n\t\t\t\t..."}, {"@style": "margin-left:1em;", "xhtml:br": [null, null, null, null], "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": [null, null, null, null, null], "#text": ".clk(clk),\n\t\t\t\t  .rst(rst),\n\t\t\t\t  .data_in(rdata),\n\t\t\t\t  //Copy-and-paste error or typo grounds data_in_security_level (in this example 0=secure, 1=non-secure) effectively promoting all data to \"secure\")\n\t\t\t\t  .data_in_security_level(1'b0),"}, "#text": "...\n\t\t\t\ttz_peripheral u_tz_peripheral(\n\t\t\t\t\n\t\t\t\t);\n\t\t\t\t..."}], "#text": "// IP definition\n\t\t\t      module tz_peripheral(clk, reset, data_in, data_in_security_level, ...);\n\t\t\t      \n\t\t\t      endmodule\n\t\t\t      // Instantiation of IP in a parent system\n\t\t\t      module soc(...)\n\t\t\t      \n\t\t\t      endmodule"}, {"@Nature": "Good", "@Language": "Verilog", "xhtml:br": [null, null, null], "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": [null, null, null, null], "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": [null, null, null, null, null], "#text": ".clk(clk),\n\t\t\t\t  .rst(rst),\n\t\t\t\t  .data_in(rdata),\n\t\t\t\t  // This port is no longer grounded, but instead driven by the appropriate signal\n\t\t\t\t  .data_in_security_level(rdata_security_level),"}, "#text": "...\n\t\t\t\ttz_peripheral u_tz_peripheral(\n\t\t\t\t\n\t\t\t\t);\n\t\t\t\t..."}, "#text": "// Instantiation of IP in a parent system\n\t\t\t      module soc(...)\n\t\t\t      \n\t\t\t      endmodule"}], "Body_Text": "In the Verilog code below, the security level input to the TrustZone aware peripheral is correctly driven by an appropriate signal instead of being grounded."}, {"Intro_Text": "Here is a code snippet from the Ariane core module in the HACK@DAC'21 Openpiton SoC [REF-1362]. \n\t\t\t\tTo ensure full functional correctness, developers connect the ports with names. However, in some cases developers forget to connect some of these ports to the desired signals in the parent module. These mistakes by developers can lead to incorrect functional behavior or, in some cases, introduce security vulnerabilities.", "Example_Code": [{"@Nature": "Bad", "@Language": "Verilog", "xhtml:br": [null, null, null, null, null], "xhtml:div": [{"@style": "margin-left:1em;", "xhtml:br": null, "#text": "..."}, {"@style": "margin-left:1em;", "xhtml:br": [null, null, null, null, null, null], "xhtml:b": [".irq_i(),", ".time_irq_i(),"], "#text": ".flush_o             ( flush_csr_ctrl ),\n\t\t\t\t\t.halt_csr_o          ( halt_csr_ctrl ),\n\t\t\t\t\t...\n\t\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\t.*"}], "#text": "...\n\t\t\t\tcsr_regfile #(\n\t\t\t\t\t\n\t\t\t\t) csr_regfile_i (\n\t\t\t\t\t\n\t\t\t\t);\n\t\t\t\t..."}, {"@Nature": "Good", "@Language": "Verilog", "xhtml:br": [null, null, null, null, null], "xhtml:div": [{"@style": "margin-left:1em;", "xhtml:br": null, "#text": "..."}, {"@style": "margin-left:1em;", "xhtml:br": [null, null, null, null, null, null], "xhtml:b": [".irq_i\t\t\t(irq_i),", ".time_irq_i\t(time_irq_i),"], "#text": ".flush_o             ( flush_csr_ctrl ),\n\t\t\t\t\t.halt_csr_o          ( halt_csr_ctrl ),\n\t\t\t\t\t...\n\t\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\t.*"}], "#text": "...\n\t\t\t\tcsr_regfile #(\n\t\t\t\t\t\n\t\t\t\t) csr_regfile_i (\n\t\t\t\t\t\n\t\t\t\t);\n\t\t\t\t..."}], "Body_Text": ["In the above example from HACK@DAC'21, since interrupt signals are not properly connected, the CSR module will fail to send notifications in the event of interrupts. Consequently, critical information in CSR registers that should be flushed or modified in response to an interrupt won't be updated. These vulnerabilities can potentially result in information leakage across various privilege levels.", "To address the aforementioned vulnerability, developers must follow a two-step approach. First, they should ensure that all module signals are properly connected. This can often be facilitated using automated tools, and many simulators and sanitizer tools issue warnings when a signal remains unconnected or floats. Second, it is imperative to validate that the signals connected to a module align with the specifications. In the provided example, the developer should establish the correct connection of interrupt signals from the parent module (Ariane core) to the child module (csr_regfile) [REF-1363]."]}]}, "References": {"Reference": [{"@External_Reference_ID": "REF-1362"}, {"@External_Reference_ID": "REF-1363"}]}, "Mapping_Notes": {"Usage": "Allowed", "Rationale": "This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.", "Comments": "Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.", "Reasons": {"Reason": {"@Type": "Acceptable-Use"}}}, "Content_History": {"Submission": {"Submission_Name": "Nicole Fern", "Submission_Organization": "Cycuity (originally submitted as Tortuga Logic)", "Submission_Date": "2020-05-22", "Submission_Version": "4.1", "Submission_ReleaseDate": "2020-02-24"}, "Modification": [{"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2020-08-20", "Modification_Version": "4.2", "Modification_ReleaseDate": "2020-08-20", "Modification_Comment": "updated Demonstrative_Examples, Description, Modes_of_Introduction, Name, Potential_Mitigations"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2022-10-13", "Modification_Version": "4.9", "Modification_ReleaseDate": "2022-10-13", "Modification_Comment": "updated Demonstrative_Examples"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2023-04-27", "Modification_Version": "4.11", "Modification_ReleaseDate": "2023-04-27", "Modification_Comment": "updated Relationships"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2023-06-29", "Modification_Version": "4.12", "Modification_ReleaseDate": "2023-06-29", "Modification_Comment": "updated Mapping_Notes"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2023-10-26", "Modification_Version": "4.13", "Modification_ReleaseDate": "2023-10-26", "Modification_Comment": "updated Demonstrative_Examples, References"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2025-12-11", "Modification_Version": "4.19", "Modification_ReleaseDate": "2025-12-11", "Modification_Comment": "updated Demonstrative_Examples, Weakness_Ordinalities"}], "Contribution": [{"@Type": "Content", "Contribution_Name": "Chen Chen, Rahul Kande, Jeyavijayan Rajendran", "Contribution_Organization": "Texas A&M University", "Contribution_Date": "2023-06-21", "Contribution_Comment": "suggested demonstrative example"}, {"@Type": "Content", "Contribution_Name": "Shaza Zeitouni, Mohamadreza Rostami, Ahmad-Reza Sadeghi", "Contribution_Organization": "Technical University of Darmstadt", "Contribution_Date": "2023-06-21", "Contribution_Comment": "suggested demonstrative example"}], "Previous_Entry_Name": {"@Date": "2020-08-20", "#text": "Hardware Block Incorrectly Connected to Larger System"}}}