{"@ID": "1296", "@Name": "Incorrect Chaining or Granularity of Debug Components", "@Abstraction": "Base", "@Structure": "Simple", "@Status": "Incomplete", "Description": "The product's debug components contain incorrect chaining or granularity of debug components.", "Extended_Description": {"xhtml:p": "Logic errors during design or synthesis could misconfigure the interconnection of the debug components, which could allow unintended access permissions.", "#text_blocks": ["Logic errors during design or synthesis could misconfigure the interconnection of the debug components, which could allow unintended access permissions."]}, "Related_Weaknesses": {"Related_Weakness": {"@Nature": "ChildOf", "@CWE_ID": "284", "@View_ID": "1000", "@Ordinal": "Primary"}}, "Weakness_Ordinalities": {"Weakness_Ordinality": {"Ordinality": "Primary"}}, "Applicable_Platforms": {"Language": [{"@Name": "Verilog", "@Prevalence": "Undetermined"}, {"@Name": "VHDL", "@Prevalence": "Undetermined"}, {"@Class": "Not Language-Specific", "@Prevalence": "Undetermined"}], "Operating_System": {"@Class": "Not OS-Specific", "@Prevalence": "Undetermined"}, "Architecture": {"@Class": "Not Architecture-Specific", "@Prevalence": "Undetermined"}, "Technology": [{"@Name": "Processor Hardware", "@Prevalence": "Undetermined"}, {"@Class": "Not Technology-Specific", "@Prevalence": "Undetermined"}]}, "Background_Details": {"Background_Detail": {"xhtml:p": "For debugging and troubleshooting a chip, several hardware design elements are often implemented, including:", "xhtml:ul": {"xhtml:li": ["Various Test Access Ports (TAPs) allow boundary scan commands to be executed.", "For scanning the internal components of a chip, there are scan cells that allow the chip to be used as a \"stimulus and response\" mechanism.", "Chipmakers might create custom methods to observe the internal components of their chips by placing various tracing hubs within their chip and creating hierarchical or interconnected structures among those hubs."]}, "#text_blocks": ["For debugging and troubleshooting a chip, several hardware design elements are often implemented, including:", "Various Test Access Ports (TAPs) allow boundary scan commands to be executed.", "For scanning the internal components of a chip, there are scan cells that allow the chip to be used as a \"stimulus and response\" mechanism.", "Chipmakers might create custom methods to observe the internal components of their chips by placing various tracing hubs within their chip and creating hierarchical or interconnected structures among those hubs."]}}, "Modes_Of_Introduction": {"Introduction": {"Phase": "Implementation", "Note": "Logic errors during design or synthesis could misconfigure the interconnection of the debug components, which could allow unintended access permissions."}}, "Common_Consequences": {"Consequence": {"Scope": ["Confidentiality", "Integrity", "Access Control", "Authentication", "Authorization", "Availability", "Accountability"], "Impact": ["Gain Privileges or Assume Identity", "Bypass Protection Mechanism", "Execute Unauthorized Code or Commands", "Modify Memory", "Modify Files or Directories"], "Likelihood": "Medium", "Note": "Depending on the access to debug component(s) erroneously granted, an attacker could use the debug component to gain additional understanding about the system to further an attack and/or execute other commands. This could compromise any security property, including the ones listed above."}}, "Detection_Methods": {"Detection_Method": [{"Method": "Architecture or Design Review", "Description": "Appropriate Post-Si tests should be carried out at various authorization levels to ensure that debug components are properly chained and accessible only to users with appropriate credentials.", "Effectiveness": "High"}, {"Method": "Dynamic Analysis with Manual Results Interpretation", "Description": "Appropriate Post-Si tests should be carried out at various authorization levels to ensure that debug components are properly chained and accessible only to users with appropriate credentials.", "Effectiveness": "High"}]}, "Potential_Mitigations": {"Mitigation": {"Phase": "Implementation", "Description": "Ensure that debug components are properly chained and their granularity is maintained at different authentication levels."}}, "Demonstrative_Examples": {"Demonstrative_Example": {"Intro_Text": "The following example shows how an attacker can take advantage of incorrect chaining or missing granularity of debug components.", "Body_Text": ["In a System-on-Chip (SoC), the user might be able to access the SoC-level TAP with a certain level of authorization. However, this access should not also grant access to all of the internal TAPs (e.g., Core). Separately, if any of the internal TAPs is also stitched to the TAP chain when it should not be because of a logic error, then an attacker can access the internal TAPs as well and execute commands there.", "As a related example, suppose there is a hierarchy of TAPs (TAP_A is connected to TAP_B and TAP_C, then TAP_B is connected to TAP_D and TAP_E, then TAP_C is connected to TAP_F and TAP_G, etc.).  Architecture mandates that the user have one set of credentials for just accessing TAP_A, another set of credentials for accessing TAP_B and TAP_C, etc. However, if, during implementation, the designer mistakenly implements a daisy-chained TAP where all the TAPs are connected in a single TAP chain without the hierarchical structure, the correct granularity of debug components is not implemented and the attacker can gain unauthorized access."]}}, "Observed_Examples": {"Observed_Example": [{"Reference": "CVE-2017-18347", "Description": "Incorrect access control in RDP Level 1 on STMicroelectronics STM32F0 series devices allows physically present attackers to extract the device's protected firmware via a special sequence of Serial Wire Debug (SWD) commands because there is a race condition between full initialization of the SWD interface and the setup of flash protection.", "Link": "https://www.cve.org/CVERecord?id=CVE-2017-18347"}, {"Reference": "CVE-2020-1791", "Description": "There is an improper authorization vulnerability in several smartphones.  The system has a logic-judging error, and, under certain scenarios, a successful exploit could allow the attacker to switch to third desktop after a series of operations in ADB mode. (Vulnerability ID: HWPSIRT-2019-10114).", "Link": "https://www.cve.org/CVERecord?id=CVE-2020-1791"}]}, "Related_Attack_Patterns": {"Related_Attack_Pattern": [{"@CAPEC_ID": "121"}, {"@CAPEC_ID": "702"}]}, "Mapping_Notes": {"Usage": "Allowed", "Rationale": "This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.", "Comments": "Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.", "Reasons": {"Reason": {"@Type": "Acceptable-Use"}}}, "Notes": {"Note": {"@Type": "Maintenance", "#text": "This entry is still under development and will continue to see updates and content improvements."}}, "Content_History": {"Submission": {"Submission_Name": "Arun Kanuparthi, Hareesh Khattri, Parbati Kumar Manna", "Submission_Organization": "Intel Corporation", "Submission_Date": "2020-05-31", "Submission_Version": "4.2", "Submission_ReleaseDate": "2020-08-20"}, "Modification": [{"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2021-07-20", "Modification_Version": "4.5", "Modification_ReleaseDate": "2021-07-20", "Modification_Comment": "updated Related_Attack_Patterns"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2022-04-28", "Modification_Version": "4.7", "Modification_ReleaseDate": "2022-04-28", "Modification_Comment": "updated Applicable_Platforms, Related_Attack_Patterns"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2022-06-28", "Modification_Version": "4.8", "Modification_ReleaseDate": "2022-06-28", "Modification_Comment": "updated Applicable_Platforms"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2023-01-31", "Modification_Version": "4.10", "Modification_ReleaseDate": "2023-01-31", "Modification_Comment": "updated Related_Attack_Patterns"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2023-04-27", "Modification_Version": "4.11", "Modification_ReleaseDate": "2023-04-27", "Modification_Comment": "updated Relationships"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2023-06-29", "Modification_Version": "4.12", "Modification_ReleaseDate": "2023-06-29", "Modification_Comment": "updated Mapping_Notes"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2025-12-11", "Modification_Version": "4.19", "Modification_ReleaseDate": "2025-12-11", "Modification_Comment": "updated Weakness_Ordinalities"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2026-10-28", "Modification_Version": "5.0", "Modification_ReleaseDate": "2026-10-28", "Modification_Comment": "updated Background_Details, Description, Modes_of_Introduction"}]}, "entry_type": "Weakness"}