{"@ID": "1298", "@Name": "Hardware Logic Contains Race Conditions", "@Abstraction": "Base", "@Structure": "Simple", "@Status": "Draft", "Description": "A race condition in the hardware logic results in undermining security guarantees of the system.", "Extended_Description": {"xhtml:p": "A race condition in logic circuits typically occurs when a logic gate gets inputs from signals that have traversed different paths while originating from the same source. Such inputs to the gate can change at slightly different times in response to a change in the source signal. This results in a timing error or a glitch (temporary or permanent) that causes the output to change to an unwanted state before settling back to the desired state. If such timing errors occur in access control logic or finite state machines that are implemented in security sensitive flows, an attacker might exploit them to circumvent existing protections."}, "Related_Weaknesses": {"Related_Weakness": {"@Nature": "ChildOf", "@CWE_ID": "362", "@View_ID": "1000", "@Ordinal": "Primary"}}, "Weakness_Ordinalities": {"Weakness_Ordinality": [{"Ordinality": "Primary"}, {"Ordinality": "Resultant"}]}, "Applicable_Platforms": {"Language": [{"@Name": "Verilog", "@Prevalence": "Undetermined"}, {"@Name": "VHDL", "@Prevalence": "Undetermined"}], "Technology": {"@Class": "System on Chip", "@Prevalence": "Undetermined"}}, "Modes_Of_Introduction": {"Introduction": [{"Phase": "Architecture and Design"}, {"Phase": "Implementation"}]}, "Common_Consequences": {"Consequence": {"Scope": "Access Control", "Impact": ["Bypass Protection Mechanism", "Gain Privileges or Assume Identity", "Alter Execution Logic"]}}, "Potential_Mitigations": {"Mitigation": [{"Phase": "Architecture and Design", "Description": "Adopting design practices that encourage designers to recognize and eliminate race conditions, such as Karnaugh maps, could result in the decrease in occurrences of race conditions."}, {"Phase": "Implementation", "Description": "Logic redundancy can be implemented along security critical paths to prevent race conditions. To avoid metastability, it is a good practice in general to default to a secure state in which access is not given to untrusted agents."}]}, "Demonstrative_Examples": {"Demonstrative_Example": [{"Intro_Text": "The code below shows a 2x1 multiplexor using logic gates. Though the code shown below results in the minimum gate solution, it is disjoint and causes glitches.", "Example_Code": [{"@Nature": "Bad", "@Language": "Verilog", "xhtml:br": [null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null], "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": [null, null], "#text": "input wire in0, in1, sel,\n\t\t\t\t\t\t\toutput wire z"}, "#text": "// 2x1 Multiplexor using logic-gates\n                        \n\t\t\t\t\t\tmodule glitchEx(\n\t\t\t\t\t\t\n\t\t\t\t\t\t);\n                        \n\t\t\t\t\t\twire not_sel;\n\t\t\t\t\t\twire and_out1, and_out2;\n\t\t\t\t\t\t\n\t\t\t\t\t\tassign not_sel = ~sel;\n\t\t\t\t\t\tassign and_out1 = not_sel & in0;\n\t\t\t\t\t\tassign and_out2 = sel & in1;\n                        \n\t\t\t\t\t\t// Buggy line of code:\n\t\t\t\t\t\tassign z = and_out1 | and_out2; // glitch in signal z\n\t\t\t\t\t\t\n\t\t\t\t\t\tendmodule"}, {"@Nature": "Good", "@Language": "Verilog", "#text": "assign z <= and_out1 or and_out2 or (in0 and in1);"}], "Body_Text": ["The buggy line of code, commented above, results in signal 'z' periodically changing to an unwanted state. Thus, any logic that references signal 'z' may access it at a time when it is in this unwanted state. This line should be replaced with the line shown below in the Good Code Snippet which results in signal 'z' remaining in a continuous, known, state. Reference for the above code, along with waveforms for simulation can be found in the references below.", "This line of code removes the glitch in signal z."]}, {"Intro_Text": {"xhtml:p": ["The example code is taken from the DMA (Direct Memory Access) module of the buggy OpenPiton SoC of HACK@DAC'21. The DMA contains a finite-state machine (FSM) for accessing the permissions using the physical memory protection (PMP) unit.", "PMP provides secure regions of physical memory against unauthorized access. It allows an operating system or a hypervisor to define a series of physical memory regions and then set permissions for those regions, such as read, write, and execute permissions. When a user tries to access a protected memory area (e.g., through DMA), PMP checks the access of a PMP address (e.g., pmpaddr_i) against its configuration (pmpcfg_i). If the access violates the defined permissions (e.g., CTRL_ABORT), the PMP can trigger a fault or an interrupt. This access check is implemented in the pmp parametrized module in the below code snippet. The below code assumes that the state of the pmpaddr_i and pmpcfg_i signals will not change during the different DMA states (i.e., CTRL_IDLE to CTRL_DONE) while processing a DMA request (via dma_ctrl_reg). The DMA state machine is implemented using a case statement (not shown in the code snippet)."]}, "Example_Code": [{"@Nature": "Bad", "@Language": "Verilog", "xhtml:br": [null, null], "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": [null, null, null, null, null], "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": [null, null, null, null, null, null, null, null, null], "xhtml:div": [{"@style": "margin-left:1em;", "xhtml:br": [null, null, null], "#text": "begin\n\t\t\t\t\t\t\t\t...\n\t\t\t\t\t\t\t\tend"}, {"@style": "margin-left:1em;", "xhtml:br": [null, null], "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": [null, null, null, null], "#text": "if (dma_ctrl_reg == CTRL_IDLE || dma_ctrl_reg == CTRL_DONE)\n\t\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t\t...\n\t\t\t\t\t\t\t\t\tend"}, "#text": "begin\n\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\tend"}, {"@style": "margin-left:1em;", "xhtml:br": [null, null, null], "#text": ".XLEN       ( 64                     ),\n\t\t\t\t\t\t\t\t.PMP_LEN    ( 54                     ),\n\t\t\t\t\t\t\t\t.NR_ENTRIES ( 16           )"}, {"@style": "margin-left:1em;", "xhtml:br": [null, null, null, null, null, null, null], "xhtml:b": ["pmpaddr_i", "pmpcfg_i"], "#text": ".addr_i        ( pmp_addr_reg        ),\n\t\t\t\t\t\t\t\t.priv_lvl_i    ( riscv::PRIV_LVL_U   ),\n\t\t\t\t\t\t\t\t.access_type_i ( pmp_access_type_reg ),\n\t\t\t\t\t\t\t\t// Configuration\n\t\t\t\t\t\t\t\t.conf_addr_i   (            ),\n\t\t\t\t\t\t\t\t.conf_i        (             ),\n\t\t\t\t\t\t\t\t.allow_o       ( pmp_data_allow      )"}], "#text": "begin: save_inputs\n\t\t\t\t\t\t\tif (!rst_ni)\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\tend // save_inputs\n\t\t\t\t\t\t\t...\n\t\t\t\t\t\t\t// Load/store PMP check\n\t\t\t\t\t\t\tpmp #(\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t) i_pmp_data (\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t);"}, "#text": "input [7:0] [16-1:0] pmpcfg_i;\n\t\t\t\t\t\tinput logic [16-1:0][53:0]     pmpaddr_i;\n\t\t\t\t\t\t...\n\t\t\t\t\t\t//// Save the input command\n  \t\t\t\t\t\talways @ (posedge clk_i or negedge rst_ni)"}, "#text": "module dma # (...)(...);\n\t\t\t\t\t...\n\t\t\t\t\t\t\n\t\t\t\t\tendmodule"}, {"@Nature": "Good", "@Language": "Verilog", "xhtml:br": [null, null], "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": [null, null, null, null, null, null, null, null], "xhtml:b": ["reg [7:0] [16-1:0] pmpcfg_reg;", "reg [16-1:0][53:0] pmpaddr_reg;"], "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": [null, null, null, null, null, null, null, null, null], "xhtml:div": [{"@style": "margin-left:1em;", "xhtml:br": [null, null, null, null, null], "xhtml:b": ["pmpaddr_reg <= 'b0 ;", "pmpcfg_reg <= 'b0 ;"], "#text": "begin\n\t\t\t\t\t\t\t\t...\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\tend"}, {"@style": "margin-left:1em;", "xhtml:br": [null, null], "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": [null, null, null, null, null, null], "xhtml:b": ["pmpaddr_reg <= pmpaddr_i;", "pmpcfg_reg <= pmpcfg_i;"], "#text": "if (dma_ctrl_reg == CTRL_IDLE || dma_ctrl_reg == CTRL_DONE) \n\t\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t\t...\n\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\tend"}, "#text": "begin\n\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\tend"}, {"@style": "margin-left:1em;", "xhtml:br": [null, null, null], "#text": ".XLEN       ( 64                     ),\n\t\t\t\t\t\t\t\t.PMP_LEN    ( 54                     ),\n\t\t\t\t\t\t\t\t.NR_ENTRIES ( 16           )"}, {"@style": "margin-left:1em;", "xhtml:br": [null, null, null, null, null, null, null], "xhtml:b": ["pmpaddr_reg", "pmpcfg_reg"], "#text": ".addr_i        ( pmp_addr_reg        ),\n\t\t\t\t\t\t\t\t.priv_lvl_i    ( riscv::PRIV_LVL_U   ), // we intend to apply filter on\n\t\t\t\t\t\t\t\t// DMA always, so choose the least privilege\n\t\t\t\t\t\t\t\t.access_type_i ( pmp_access_type_reg ),\n\t\t\t\t\t\t\t\t// Configuration\n\t\t\t\t\t\t\t\t.conf_addr_i   (            ),\n\t\t\t\t\t\t\t\t.conf_i        (             ),\n\t\t\t\t\t\t\t\t.allow_o       ( pmp_data_allow      )"}], "#text": "begin: save_inputs\n\t\t\t\t\t\t\tif (!rst_ni)\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\telse \n\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\tend // save_inputs\n\t\t\t\t\t\t\t...\n\t\t\t\t\t\t\t// Load/store PMP check\n\t\t\t\t\t\t\tpmp #(\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t) i_pmp_data (\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t);"}, "#text": "input [7:0] [16-1:0] pmpcfg_i;   \n\t\t\t\t\t\tinput logic [16-1:0][53:0]     pmpaddr_i;\n\t\t\t\t\t\t...\n\t\t\t\t\t\t\n\t\t\t\t\t\t\n\t\t\t\t\t\t...\n\t\t\t\t\t\t//// Save the input command\n\t\t\t\t\t\talways @ (posedge clk_i or negedge rst_ni)"}, "#text": "module dma # (...)(...);\n\t\t\t\t\t...\n\t\t\t\t\t\t\n\t\t\t\t\tendmodule"}], "Body_Text": {"xhtml:p": ["However, the above code [REF-1394] allows the values of pmpaddr_i and pmpcfg_i to be changed through DMA's input ports. This causes a race condition and will enable attackers to access sensitive addresses that the configuration is not associated with.", "Attackers can initialize the DMA access process (CTRL_IDLE) using pmpcfg_i for a non-privileged PMP address (pmpaddr_i). Then during the loading state (CTRL_LOAD), attackers can replace the non-privileged address in pmpaddr_i with a privileged address without the requisite authorized access configuration.", "To fix this issue (see [REF-1395]), the value of the pmpaddr_i and pmpcfg_i signals should be stored in local registers (pmpaddr_reg and pmpcfg_reg at the start of the DMA access process and the pmp module should reference those registers instead of the signals directly. The values of the registers can only be updated at the start (CTRL_IDLE) or the end (CTRL_DONE) of the DMA access process, which prevents attackers from changing the PMP address in the middle of the DMA access process."]}}]}, "Related_Attack_Patterns": {"Related_Attack_Pattern": {"@CAPEC_ID": "26"}}, "References": {"Reference": [{"@External_Reference_ID": "REF-1115"}, {"@External_Reference_ID": "REF-1116"}, {"@External_Reference_ID": "REF-1394"}, {"@External_Reference_ID": "REF-1395"}]}, "Mapping_Notes": {"Usage": "Allowed", "Rationale": "This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.", "Comments": "Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.", "Reasons": {"Reason": {"@Type": "Acceptable-Use"}}}, "Content_History": {"Submission": {"Submission_Name": "Arun Kanuparthi, Hareesh Khattri, Parbati Kumar Manna, Narasimha Kumar V Mangipudi", "Submission_Organization": "Intel Corporation", "Submission_Date": "2020-02-10", "Submission_Version": "4.2", "Submission_ReleaseDate": "2020-08-20"}, "Modification": [{"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2021-07-20", "Modification_Version": "4.5", "Modification_ReleaseDate": "2021-07-20", "Modification_Comment": "updated Related_Attack_Patterns"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2023-04-27", "Modification_Version": "4.11", "Modification_ReleaseDate": "2023-04-27", "Modification_Comment": "updated Relationships"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2023-06-29", "Modification_Version": "4.12", "Modification_ReleaseDate": "2023-06-29", "Modification_Comment": "updated Mapping_Notes"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2024-02-29", "Modification_Version": "4.14", "Modification_ReleaseDate": "2024-02-29", "Modification_Comment": "updated Demonstrative_Examples, References"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2025-12-11", "Modification_Version": "4.19", "Modification_ReleaseDate": "2025-12-11", "Modification_Comment": "updated Weakness_Ordinalities"}], "Contribution": [{"@Type": "Content", "Contribution_Name": "Chen Chen, Rahul Kande, Jeyavijayan Rajendran", "Contribution_Organization": "Texas A&M University", "Contribution_Date": "2023-11-29", "Contribution_Comment": "suggested demonstrative example"}, {"@Type": "Content", "Contribution_Name": "Shaza Zeitouni, Mohamadreza Rostami, Ahmad-Reza Sadeghi", "Contribution_Organization": "Technical University of Darmstadt", "Contribution_Date": "2023-11-29", "Contribution_Comment": "suggested demonstrative example"}]}}