{"@ID": "1431", "@Name": "Driving Intermediate Cryptographic State/Results to Hardware Module Outputs", "@Abstraction": "Base", "@Structure": "Simple", "@Status": "Incomplete", "Description": "The product uses a hardware module implementing a cryptographic\n\t\t  algorithm that writes sensitive information about the intermediate\n\t\t  state or results of its cryptographic operations via one of its output\n\t\t  wires (typically the output port containing the final result).", "Related_Weaknesses": {"Related_Weakness": [{"@Nature": "ChildOf", "@CWE_ID": "201", "@View_ID": "1000", "@Ordinal": "Primary"}, {"@Nature": "PeerOf", "@CWE_ID": "497", "@View_ID": "1000"}, {"@Nature": "ChildOf", "@CWE_ID": "325", "@View_ID": "1000"}, {"@Nature": "PeerOf", "@CWE_ID": "1420", "@View_ID": "1000"}, {"@Nature": "PeerOf", "@CWE_ID": "1258", "@View_ID": "1000"}]}, "Weakness_Ordinalities": {"Weakness_Ordinality": {"Ordinality": "Primary"}}, "Applicable_Platforms": {"Language": {"@Class": "Not Language-Specific", "@Prevalence": "Undetermined"}, "Architecture": {"@Class": "Not Architecture-Specific", "@Prevalence": "Undetermined"}, "Technology": {"@Class": "System on Chip", "@Prevalence": "Undetermined"}}, "Modes_Of_Introduction": {"Introduction": {"Phase": "Implementation", "Note": {"xhtml:p": "This can occur when intermediate cryptographic states are\n\t\t      directly assigned to output wires or ports.", "#text_blocks": ["This can occur when intermediate cryptographic states are\n\t\t      directly assigned to output wires or ports."]}}}, "Common_Consequences": {"Consequence": {"Scope": "Confidentiality", "Impact": ["Read Memory", "Read Application Data"], "Likelihood": "Unknown", "Note": {"xhtml:p": "Mathematically sound cryptographic algorithms rely on their\n\t\t\t    correct implementation for security. These assumptions might break when a\n\t\t\t    hardware crypto module leaks intermediate encryption states or results\n\t\t\t    such that they can be observed by an adversary. If intermediate state\n\t\t\t    is observed, it might be possible for an attacker to identify the\n\t\t\t    secrets used in the cryptographic operation.", "#text_blocks": ["Mathematically sound cryptographic algorithms rely on their\n\t\t\t    correct implementation for security. These assumptions might break when a\n\t\t\t    hardware crypto module leaks intermediate encryption states or results\n\t\t\t    such that they can be observed by an adversary. If intermediate state\n\t\t\t    is observed, it might be possible for an attacker to identify the\n\t\t\t    secrets used in the cryptographic operation."]}}}, "Detection_Methods": {"Detection_Method": [{"Method": "Automated Static Analysis - Source Code", "Description": {"xhtml:p": "Automated static analysis can find some instances of this\n\t\t\t    weakness by analyzing source register-transfer level (RTL) code\n\t\t\t    without having to simulate it or analyze it with a formal verification\n\t\t\t    engine. Typically, this is done by building a model of data flow and\n\t\t\t    control flow, then searching for potentially-vulnerable patterns that\n\t\t\t    connect \"sources\" (signals with intermediate cryptographic\n\t\t\t    state/results) with \"sinks\" (hardware module outputs and other signals\n\t\t\t    outside of trusted cryptographic zone) without any control flow.", "#text_blocks": ["Automated static analysis can find some instances of this\n\t\t\t    weakness by analyzing source register-transfer level (RTL) code\n\t\t\t    without having to simulate it or analyze it with a formal verification\n\t\t\t    engine. Typically, this is done by building a model of data flow and\n\t\t\t    control flow, then searching for potentially-vulnerable patterns that\n\t\t\t    connect \"sources\" (signals with intermediate cryptographic\n\t\t\t    state/results) with \"sinks\" (hardware module outputs and other signals\n\t\t\t    outside of trusted cryptographic zone) without any control flow."]}, "Effectiveness": "High", "Effectiveness_Notes": {"xhtml:p": "Static code analysis can sometimes lead to false positives.", "#text_blocks": ["Static code analysis can sometimes lead to false positives."]}}, {"Method": "Simulation / Emulation", "Description": {"xhtml:p": "Simulation/emulation based analysis can find some instances of\n\t\t\t    this weakness by simulating source register-transfer level (RTL) code\n\t\t\t    along with a set of assertions that incorporate the simulated values\n\t\t\t    of relevant design signals. Typically, these assertions will capture\n\t\t\t    desired or undesired behavior. Analysis can be improved by using\n\t\t\t    simulation-based information flow tracking (IFT) to more precisely\n\t\t\t    detect unexpected results.", "#text_blocks": ["Simulation/emulation based analysis can find some instances of\n\t\t\t    this weakness by simulating source register-transfer level (RTL) code\n\t\t\t    along with a set of assertions that incorporate the simulated values\n\t\t\t    of relevant design signals. Typically, these assertions will capture\n\t\t\t    desired or undesired behavior. Analysis can be improved by using\n\t\t\t    simulation-based information flow tracking (IFT) to more precisely\n\t\t\t    detect unexpected results."]}, "Effectiveness": "High", "Effectiveness_Notes": {"xhtml:p": "Simulation/emulation based analysis can sometimes lead to false\n\t\t\t    negatives if the testbench does not drive the design to a design state\n\t\t\t    in which the assertion would fail.", "#text_blocks": ["Simulation/emulation based analysis can sometimes lead to false\n\t\t\t    negatives if the testbench does not drive the design to a design state\n\t\t\t    in which the assertion would fail."]}}, {"Method": "Formal Verification", "Description": {"xhtml:p": ["Formal verification can find some instances of this weakness by\n\t\t\t    exhaustively analyzing whether a given assertion holds true for a\n\t\t\t    given hardware design specified in register-transfer level (RTL)\n\t\t\t    code. Typically, these assertions will capture desired or undesired\n\t\t\t    behavior. For this weakness, an assertion should check for undesired\n\t\t\t    behavior in which one output is a signal that captures when a\n\t\t\t    cryptographic algorithm has completely finished; another output is a\n\t\t\t    signal with intermediate cryptographic state/results; and there is an\n\t\t\t    assignment to a hardware module output or other signal outside of a\n\t\t\t    trusted cryptographic zone.", "Alternatively, when using a formal IFT verification, the same\n\t\t\t    undesired behavior can be detected by checking if computation results\n\t\t\t    can ever leak to an output when the cryptographic result is not\n\t\t\t    complete."], "#text_blocks": ["Formal verification can find some instances of this weakness by\n\t\t\t    exhaustively analyzing whether a given assertion holds true for a\n\t\t\t    given hardware design specified in register-transfer level (RTL)\n\t\t\t    code. Typically, these assertions will capture desired or undesired\n\t\t\t    behavior. For this weakness, an assertion should check for undesired\n\t\t\t    behavior in which one output is a signal that captures when a\n\t\t\t    cryptographic algorithm has completely finished; another output is a\n\t\t\t    signal with intermediate cryptographic state/results; and there is an\n\t\t\t    assignment to a hardware module output or other signal outside of a\n\t\t\t    trusted cryptographic zone.", "Alternatively, when using a formal IFT verification, the same\n\t\t\t    undesired behavior can be detected by checking if computation results\n\t\t\t    can ever leak to an output when the cryptographic result is not\n\t\t\t    complete."]}, "Effectiveness": "High", "Effectiveness_Notes": {"xhtml:p": "Formal verification may not scale for RTL designs with a large state space.", "#text_blocks": ["Formal verification may not scale for RTL designs with a large state space."]}}, {"Method": "Manual Analysis", "Description": {"xhtml:p": "Manual analysis can find some instances of this weakness by\n\t\t\t    manually reviewing relevant lines of source register-transfer level\n\t\t\t    (RTL) code to detect potentially-vulnerable patterns. Typically, the\n\t\t\t    reviewer will trace the sequence of assignments that connect \"sources\"\n\t\t\t    (signals with intermediate cryptographic state/results) with \"sinks\"\n\t\t\t    (hardware module outputs and other signals outside of trusted\n\t\t\t    cryptographic zone). If this sequence of assignments is missing\n\t\t\t    adequate control flow, then the weakness is likely to exist.", "#text_blocks": ["Manual analysis can find some instances of this weakness by\n\t\t\t    manually reviewing relevant lines of source register-transfer level\n\t\t\t    (RTL) code to detect potentially-vulnerable patterns. Typically, the\n\t\t\t    reviewer will trace the sequence of assignments that connect \"sources\"\n\t\t\t    (signals with intermediate cryptographic state/results) with \"sinks\"\n\t\t\t    (hardware module outputs and other signals outside of trusted\n\t\t\t    cryptographic zone). If this sequence of assignments is missing\n\t\t\t    adequate control flow, then the weakness is likely to exist."]}, "Effectiveness": "Opportunistic", "Effectiveness_Notes": {"xhtml:p": "Manual analysis of source code is prone to errors (false\n\t\t\t    positives and false negatives) and highly opportunistic.", "#text_blocks": ["Manual analysis of source code is prone to errors (false\n\t\t\t    positives and false negatives) and highly opportunistic."]}}]}, "Potential_Mitigations": {"Mitigation": [{"Phase": "Architecture and Design", "Description": {"xhtml:p": "Designers/developers\n\t\t\t    should add or modify existing control flow\n\t\t\t    logic along any data flow paths that\n\t\t\t    connect \"sources\" (signals with\n\t\t\t    intermediate cryptographic state/results)\n\t\t\t    with \"sinks\" (hardware module outputs and\n\t\t\t    other signals outside of trusted\n\t\t\t    cryptographic zone). The control flow\n\t\t\t    logic should only allow cryptographic\n\t\t\t    results to be driven to \"sinks\" when\n\t\t\t    appropriate conditions are satisfied\n\t\t\t    (typically when the final result for a\n\t\t\t    cryptographic operation has been\n\t\t\t    generated). When the appropriate\n\t\t\t    conditions are not satisfied (i.e., before\n\t\t\t    or during a cryptographic operation), the\n\t\t\t    control flow logic should drive a safe\n\t\t\t    default value to\n\t\t\t    \"sinks\".", "#text_blocks": ["Designers/developers\n\t\t\t    should add or modify existing control flow\n\t\t\t    logic along any data flow paths that\n\t\t\t    connect \"sources\" (signals with\n\t\t\t    intermediate cryptographic state/results)\n\t\t\t    with \"sinks\" (hardware module outputs and\n\t\t\t    other signals outside of trusted\n\t\t\t    cryptographic zone). The control flow\n\t\t\t    logic should only allow cryptographic\n\t\t\t    results to be driven to \"sinks\" when\n\t\t\t    appropriate conditions are satisfied\n\t\t\t    (typically when the final result for a\n\t\t\t    cryptographic operation has been\n\t\t\t    generated). When the appropriate\n\t\t\t    conditions are not satisfied (i.e., before\n\t\t\t    or during a cryptographic operation), the\n\t\t\t    control flow logic should drive a safe\n\t\t\t    default value to\n\t\t\t    \"sinks\"."]}, "Effectiveness": "High"}, {"Phase": "Implementation", "Description": {"xhtml:p": "Designers/developers\n\t\t\t    should add or modify existing control flow\n\t\t\t    logic along any data flow paths that\n\t\t\t    connect \"sources\" (signals with\n\t\t\t    intermediate cryptographic state/results)\n\t\t\t    with \"sinks\" (hardware module outputs and\n\t\t\t    other signals outside of trusted\n\t\t\t    cryptographic zone). The control flow\n\t\t\t    logic should only allow cryptographic\n\t\t\t    results to be driven to \"sinks\" when\n\t\t\t    appropriate conditions are satisfied\n\t\t\t    (typically when the final result for a\n\t\t\t    cryptographic operation has been\n\t\t\t    generated). When the appropriate\n\t\t\t    conditions are not satisfied (i.e., before\n\t\t\t    or during a cryptographic operation), the\n\t\t\t    control flow logic should drive a safe\n\t\t\t    default value to\n\t\t\t    \"sinks\".", "#text_blocks": ["Designers/developers\n\t\t\t    should add or modify existing control flow\n\t\t\t    logic along any data flow paths that\n\t\t\t    connect \"sources\" (signals with\n\t\t\t    intermediate cryptographic state/results)\n\t\t\t    with \"sinks\" (hardware module outputs and\n\t\t\t    other signals outside of trusted\n\t\t\t    cryptographic zone). The control flow\n\t\t\t    logic should only allow cryptographic\n\t\t\t    results to be driven to \"sinks\" when\n\t\t\t    appropriate conditions are satisfied\n\t\t\t    (typically when the final result for a\n\t\t\t    cryptographic operation has been\n\t\t\t    generated). When the appropriate\n\t\t\t    conditions are not satisfied (i.e., before\n\t\t\t    or during a cryptographic operation), the\n\t\t\t    control flow logic should drive a safe\n\t\t\t    default value to\n\t\t\t    \"sinks\"."]}, "Effectiveness": "High"}]}, "Demonstrative_Examples": {"Demonstrative_Example": {"Intro_Text": {"xhtml:p": "The following SystemVerilog code is a crypto module that takes input\n\t\t\t    data and encrypts it by processing the data through multiple\n\t\t\t    encryption rounds. Note: this example is derived from [REF-1469].", "#text_blocks": ["The following SystemVerilog code is a crypto module that takes input\n\t\t\t    data and encrypts it by processing the data through multiple\n\t\t\t    encryption rounds. Note: this example is derived from [REF-1469]."]}, "Example_Code": [{"@Nature": "Bad", "@Language": "SystemVerilog", "xhtml:br": [null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null], "xhtml:div": [{"@style": "margin-left:1em;", "xhtml:br": [null, null, null, null, null], "#text": "03 |     input  clk,\n\t\t\t\t04 |     input  rst,\n\t\t\t\t05 |     input  [127:0] data_i,\n\t\t\t\t06 |     output [127:0] data_o,\n\t\t\t\t07 |     output valid"}, {"@style": "margin-left:1em;", "xhtml:br": [null, null, null, null, null, null, null], "#text": "16 |     .clk     (clk),\n\t\t\t\t17 |     .rst     (rst),\n\t\t\t\t18 |     .round_i (round_id_q  ),\n\t\t\t\t19 |     .key_i   (key_state_q ),\n\t\t\t\t20 |     .data_i  (data_state_q),\n\t\t\t\t21 |     .key_o   (key_state_d ),\n\t\t\t\t22 |     .data_o  (data_state_d)"}, {"@style": "margin-left:1em;", "xhtml:br": [null, null, null, null], "xhtml:div": [{"@style": "margin-left:1em;", "xhtml:br": [null, null, null], "#text": "27 |         data_state_q <= 0;\n\t\t\t\t  28 |         key_state_q  <= 0;\n\t\t\t\t  29 |         round_id_q   <= 0;"}, {"@style": "margin-left:1em;", "xhtml:br": [null, null], "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": [null, null, null, null, null], "xhtml:div": [{"@style": "margin-left:1em;", "xhtml:br": [null, null, null], "#text": "34 |                 data_state_q <= 0;\n\t\t\t\t      35 |                 key_state_q  <= 0;\n\t\t\t\t      36 |                 round_id_q   <= 0;"}, {"@style": "margin-left:1em;", "xhtml:br": [null, null, null], "#text": "40 |                 data_state_q <= data_state_d;\n\t\t\t\t      41 |                 key_state_q  <= key_state_d;\n\t\t\t\t      42 |                 round_id_q   <= round_id_q + 1;"}], "#text": "33 |             total_rounds: begin\n\t\t\t\t    \n\t\t\t\t    37 |             end\n\t\t\t\t    38 |\n\t\t\t\t    39 |             default: begin\n\t\t\t\t    \n\t\t\t\t    43 |             end"}, "#text": "32 |         case (round_id_q)\n\t\t\t\t  \n\t\t\t\t  44 |         endcase"}], "#text": "26 |     if (rst) begin\n\t\t\t\t\n\t\t\t\t30 |     end\n\t\t\t\t31 |     else begin\n\t\t\t\t\n\t\t\t\t45 |     end"}], "#text": "01 | module crypto_core_with_leakage\n\t\t\t      02 | (\n\t\t\t      \n\t\t\t      08 | );\n\t\t\t      09 |\n\t\t\t      10 | localparam int total_rounds = 10;\n\t\t\t      11 | logic [3:0]   round_id_q;\n\t\t\t      12 | logic [127:0] data_state_q, data_state_d;\n\t\t\t      13 | logic [127:0] key_state_q, key_state_d;\n\t\t\t      14 |\n\t\t\t      15 | crypto_algo_round u_algo_round (\n\t\t\t      \n\t\t\t      23 | );\n\t\t\t      24 |\n\t\t\t      25 | always @(posedge clk) begin\n\t\t\t      \n\t\t\t      46 | end\n\t\t\t      47 |\n\t\t\t      48 | assign valid  = (round_id_q == total_rounds) ? 1'b1 : 1'b0;\n\t\t\t      49 |\n\t\t\t      50 | assign data_o = data_state_q;\n\t\t\t      51 |\n\t\t\t      52 | endmodule", "#text_blocks": ["01 | module crypto_core_with_leakage", "02 | (", "03 |     input  clk,", "04 |     input  rst,", "05 |     input  [127:0] data_i,", "06 |     output [127:0] data_o,", "07 |     output valid", "08 | );", "09 |", "10 | localparam int total_rounds = 10;", "11 | logic [3:0]   round_id_q;", "12 | logic [127:0] data_state_q, data_state_d;", "13 | logic [127:0] key_state_q, key_state_d;", "14 |", "15 | crypto_algo_round u_algo_round (", "16 |     .clk     (clk),", "17 |     .rst     (rst),", "18 |     .round_i (round_id_q  ),", "19 |     .key_i   (key_state_q ),", "20 |     .data_i  (data_state_q),", "21 |     .key_o   (key_state_d ),", "22 |     .data_o  (data_state_d)", "23 | );", "24 |", "25 | always @(posedge clk) begin", "26 |     if (rst) begin", "27 |         data_state_q <= 0;", "28 |         key_state_q  <= 0;", "29 |         round_id_q   <= 0;", "30 |     end", "31 |     else begin", "32 |         case (round_id_q)", "33 |             total_rounds: begin", "34 |                 data_state_q <= 0;", "35 |                 key_state_q  <= 0;", "36 |                 round_id_q   <= 0;", "37 |             end", "38 |", "39 |             default: begin", "40 |                 data_state_q <= data_state_d;", "41 |                 key_state_q  <= key_state_d;", "42 |                 round_id_q   <= round_id_q + 1;", "43 |             end", "44 |         endcase", "45 |     end", "46 | end", "47 |", "48 | assign valid  = (round_id_q == total_rounds) ? 1'b1 : 1'b0;", "49 |", "50 | assign data_o = data_state_q;", "51 |", "52 | endmodule"]}, {"@Nature": "Good", "@Language": "SystemVerilog", "xhtml:br": [null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null], "xhtml:div": [{"@style": "margin-left:1em;", "xhtml:br": [null, null, null, null, null, null], "#text": "03 |     input  clk,\n\t\t\t\t04 |     input  rst,\n\t\t\t\t05 |     input  [127:0] data_i,\n\t\t\t\t06 |     output [127:0] data_o,\n\t\t\t\t07 |     output valid\n\t\t\t\t08 | );"}, {"@style": "margin-left:1em;", "xhtml:br": [null, null, null, null, null, null, null], "#text": "16 |     .clk     (clk),\n\t\t\t\t17 |     .rst     (rst),\n\t\t\t\t18 |     .round_i (round_id_q  ),\n\t\t\t\t19 |     .key_i   (key_state_q ),\n\t\t\t\t20 |     .data_i  (data_state_q),\n\t\t\t\t21 |     .key_o   (key_state_d ),\n\t\t\t\t22 |     .data_o  (data_state_d)"}, {"@style": "margin-left:1em;", "xhtml:br": [null, null, null, null], "xhtml:div": [{"@style": "margin-left:1em;", "xhtml:br": [null, null, null], "#text": "27 |         data_state_q <= 0;\n\t\t\t\t  28 |         key_state_q  <= 0;\n\t\t\t\t  29 |         round_id_q   <= 0;"}, {"@style": "margin-left:1em;", "xhtml:br": [null, null], "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": [null, null, null, null, null], "xhtml:div": [{"@style": "margin-left:1em;", "xhtml:br": [null, null, null], "#text": "34 |                 data_state_q <= 0;\n\t\t\t\t      35 |                 key_state_q  <= 0;\n\t\t\t\t      36 |                 round_id_q   <= 0;"}, {"@style": "margin-left:1em;", "xhtml:br": [null, null, null], "#text": "40 |                 data_state_q <= data_state_d;\n\t\t\t\t      41 |                 key_state_q  <= key_state_d;\n\t\t\t\t      42 |                 round_id_q   <= round_id_q + 1;"}], "#text": "33 |             total_rounds: begin\n\t\t\t\t    \n\t\t\t\t    37 |             end\n\t\t\t\t    38 |\n\t\t\t\t    39 |             default: begin\n\t\t\t\t    \n\t\t\t\t    43 |             end"}, "#text": "32 |         case (round_id_q)\n\t\t\t\t  \n\t\t\t\t  44 |         endcase"}], "#text": "26 |     if (rst) begin\n\t\t\t\t\n\t\t\t\t30 |     end\n\t\t\t\t31 |     else begin\n\t\t\t\t\n\t\t\t\t45 |     end"}], "#text": "01 | module crypto_core_without_leakage\n\t\t\t      02 | (\n\t\t\t      \n\t\t\t      09 |\n\t\t\t      10 | localparam int total_rounds = 10;\n\t\t\t      11 | logic [3:0]   round_id_q;\n\t\t\t      12 | logic [127:0] data_state_q, data_state_d;\n\t\t\t      13 | logic [127:0] key_state_q, key_state_d;\n\t\t\t      14 |\n\t\t\t      15 | crypto_algo_round u_algo_round (\n\t\t\t      \n\t\t\t      23 | );\n\t\t\t      24 |\n\t\t\t      25 | always @(posedge clk) begin\n\t\t\t      \n\t\t\t      46 | end\n\t\t\t      47 |\n\t\t\t      48 | assign valid  = (round_id_q == total_rounds) ? 1'b1 : 1'b0;\n\t\t\t      49 |\n\t\t\t      50 | assign data_o = (valid) ? data_state_q : 0;\n\t\t\t      51 |\n\t\t\t      52 | endmodule", "#text_blocks": ["01 | module crypto_core_without_leakage", "02 | (", "03 |     input  clk,", "04 |     input  rst,", "05 |     input  [127:0] data_i,", "06 |     output [127:0] data_o,", "07 |     output valid", "08 | );", "09 |", "10 | localparam int total_rounds = 10;", "11 | logic [3:0]   round_id_q;", "12 | logic [127:0] data_state_q, data_state_d;", "13 | logic [127:0] key_state_q, key_state_d;", "14 |", "15 | crypto_algo_round u_algo_round (", "16 |     .clk     (clk),", "17 |     .rst     (rst),", "18 |     .round_i (round_id_q  ),", "19 |     .key_i   (key_state_q ),", "20 |     .data_i  (data_state_q),", "21 |     .key_o   (key_state_d ),", "22 |     .data_o  (data_state_d)", "23 | );", "24 |", "25 | always @(posedge clk) begin", "26 |     if (rst) begin", "27 |         data_state_q <= 0;", "28 |         key_state_q  <= 0;", "29 |         round_id_q   <= 0;", "30 |     end", "31 |     else begin", "32 |         case (round_id_q)", "33 |             total_rounds: begin", "34 |                 data_state_q <= 0;", "35 |                 key_state_q  <= 0;", "36 |                 round_id_q   <= 0;", "37 |             end", "38 |", "39 |             default: begin", "40 |                 data_state_q <= data_state_d;", "41 |                 key_state_q  <= key_state_d;", "42 |                 round_id_q   <= round_id_q + 1;", "43 |             end", "44 |         endcase", "45 |     end", "46 | end", "47 |", "48 | assign valid  = (round_id_q == total_rounds) ? 1'b1 : 1'b0;", "49 |", "50 | assign data_o = (valid) ? data_state_q : 0;", "51 |", "52 | endmodule"]}], "Body_Text": [{"xhtml:p": "In line 50 above, data_state_q is assigned to data_o. Since data_state_q\n\t\t\t    contains intermediate state/results, this allows an attacker to obtain\n\t\t\t    these results through data_o.", "#text_blocks": ["In line 50 above, data_state_q is assigned to data_o. Since data_state_q\n\t\t\t    contains intermediate state/results, this allows an attacker to obtain\n\t\t\t    these results through data_o."]}, {"xhtml:p": "In line 50 of the fixed logic below,\n\t\t\t      while \"data_state_q\" does not contain the final result, \n\t\t\t      a \"sanitizing\" mechanism drives a safe default value (i.e., 0) to\n\t\t\t      \"data_o\" instead of the value of \"data_state_q\".\n\t\t\t      In doing so, the mechanism prevents\n\t\t\t      the exposure of intermediate state/results which could be used to\n\t\t\t      break soundness of the cryptographic operation being performed. A\n\t\t\t      real-world example of this weakness and mitigation can be seen in a\n\t\t\t      pull request that was submitted to the OpenTitan Github repository\n\t\t\t      [REF-1469].", "#text_blocks": ["In line 50 of the fixed logic below,\n\t\t\t      while \"data_state_q\" does not contain the final result, \n\t\t\t      a \"sanitizing\" mechanism drives a safe default value (i.e., 0) to\n\t\t\t      \"data_o\" instead of the value of \"data_state_q\".\n\t\t\t      In doing so, the mechanism prevents\n\t\t\t      the exposure of intermediate state/results which could be used to\n\t\t\t      break soundness of the cryptographic operation being performed. A\n\t\t\t      real-world example of this weakness and mitigation can be seen in a\n\t\t\t      pull request that was submitted to the OpenTitan Github repository\n\t\t\t      [REF-1469]."]}]}}, "References": {"Reference": [{"@External_Reference_ID": "REF-1469"}, {"@External_Reference_ID": "REF-1470"}, {"@External_Reference_ID": "REF-1471"}, {"@External_Reference_ID": "REF-1472"}, {"@External_Reference_ID": "REF-1473"}]}, "Mapping_Notes": {"Usage": "Allowed", "Rationale": "This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.", "Comments": "Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.", "Reasons": {"Reason": {"@Type": "Acceptable-Use"}}}, "Content_History": {"Submission": {"Submission_Name": "Andres Meza", "Submission_Organization": "University of California, San Diego", "Submission_Date": "2022-08-15", "Submission_Version": "4.17", "Submission_ReleaseDate": "2025-04-03"}, "Modification": [{"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2025-09-09", "Modification_Version": "4.18", "Modification_ReleaseDate": "2025-09-09", "Modification_Comment": "updated Relationships"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2025-12-11", "Modification_Version": "4.19", "Modification_ReleaseDate": "2025-12-11", "Modification_Comment": "updated Weakness_Ordinalities"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2026-10-28", "Modification_Version": "5.0", "Modification_ReleaseDate": "2026-10-28", "Modification_Comment": "updated Demonstrative_Examples, Detection_Factors, Relationships"}]}, "entry_type": "Weakness"}