CWE-1199
Grouping ProhibitedGeneral Circuit and Logic Design Concerns
Status: Draft
Weaknesses in this category are related to hardware-circuit design and logic (e.g., CMOS transistors, finite state machines, and registers) as well as issues related to hardware description languages such as System Verilog and VHDL.
Grouping entries organize the catalogue and should not be used to map the root cause of a vulnerability.
Mapping guidance
This entry is a Grouping. Using groupings for mapping has been discouraged since 2019. They are informal organizational groupings of weaknesses that can help CWE users with data aggregation, navigation, and browsing. However, they are not weaknesses in themselves.
See member weaknesses of this category.
Relationships and members
Content history
updated Relationships
updated Relationships
updated Relationships
updated Mapping_Notes
updated Mapping_Notes
updated Mapping_Notes, Relationships, Type
0 vulnerabilities reference this CWE, most recent first.
No vulnerabilities reference this CWE.
No mitigation information available for this CWE.
No CAPEC attack patterns related to this CWE.