Common Weakness Enumeration

CWE-1248

Weakness Allowed

Semiconductor Defects in Hardware Logic with Security-Sensitive Implications

Abstraction: Base · Status: Incomplete

The security-sensitive hardware module contains semiconductor defects.

Mapping guidance

This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.

Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.

Relationships and members
ChildOf: CWE-693 · View CWE-1000
Modes of introduction
Manufacturing

May be introduced due to issues in the manufacturing environment or improper handling of components, for example.

Operation

May be introduced by improper handling or usage outside of rated operating environments (temperature, humidity, etc.)

Content history
Submission: Arun Kanuparthi, Hareesh Khattri, Parbati Kumar Manna, Narasimha Kumar V Mangipudi · Intel Corporation · 2020-02-12 · CWE 4.0
Modification: CWE Content Team · MITRE · 2020-08-20 · CWE 4.2

updated Modes_of_Introduction, Related_Attack_Patterns

Modification: CWE Content Team · MITRE · 2022-06-28 · CWE 4.8

updated Relationships

Modification: CWE Content Team · MITRE · 2023-01-31 · CWE 4.10

updated Related_Attack_Patterns, Relationships

Modification: CWE Content Team · MITRE · 2023-04-27 · CWE 4.11

updated Description, References, Relationships

Modification: CWE Content Team · MITRE · 2023-06-29 · CWE 4.12

updated Mapping_Notes

Modification: CWE Content Team · MITRE · 2025-12-11 · CWE 4.19

updated Common_Consequences, Description, Weakness_Ordinalities

Modification: CWE Content Team · MITRE · 2026-10-28 · CWE 5.0

updated Background_Details, Common_Consequences, Description

0 vulnerabilities reference this CWE, most recent first.

No vulnerabilities reference this CWE.

Mitigation
Testing

While semiconductor-manufacturing companies implement several mechanisms to continuously improve the semiconductor manufacturing process to ensure reduction of defects, some defects can only be fixed after manufacturing. Post-manufacturing testing of silicon die is critical. Fault models such as stuck-at-0 or stuck-at-1 must be used to develop post-manufacturing test cases and achieve good coverage. Once the silicon packaging is done, extensive post-silicon testing must be performed to ensure that hardware logic implementing security functionalities is defect-free.

Mitigation
Operation

Operating the hardware outside device specification, such as at extremely high temperatures, voltage, etc., accelerates semiconductor degradation and results in defects. When these defects manifest as faults in security-critical, hardware modules, it results in compromise of security guarantees. Thus, operating the device within the specification is important.

CAPEC-624: Hardware Fault Injection

The adversary uses disruptive signals or events, or alters the physical environment a device operates in, to cause faulty behavior in electronic devices. This can include electromagnetic pulses, laser pulses, clock glitches, ambient temperature extremes, and more. When performed in a controlled manner on devices performing cryptographic operations, this faulty behavior can be exploited to derive secret key information.

CAPEC-625: Mobile Device Fault Injection

Fault injection attacks against mobile devices use disruptive signals or events (e.g. electromagnetic pulses, laser pulses, clock glitches, etc.) to cause faulty behavior. When performed in a controlled manner on devices performing cryptographic operations, this faulty behavior can be exploited to derive secret key information. Although this attack usually requires physical control of the mobile device, it is non-destructive, and the device can be used after the attack without any indication that secret keys were compromised.