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6 vulnerabilities found for Cortex-A710 by Arm
CVE-2025-10263 (GCVE-0-2025-10263)
Vulnerability from nvd – Published: 2026-06-09 09:23 – Updated: 2026-07-03 12:05
VLAI
Summary
Arm C1-Ultra, C1-Premium, Neoverse V3 & V3AE, Neoverse V2, Neoverse V1, Neoverse-N2, Neoverse-N1, Cortex-X925, Cortex-X4, Cortex-X3, Cortex-X2, Cortex-X1 & X1C, Cortex-A710, Cortex-A78, A78AE & A78C, Cortex-A77, Cortex-A76 & A76A may allow writes to resources owned by a higher exception level.
Severity
9.1 (Critical)
8.4 (High)
SSVC
Exploitation: none
Automatable: yes
Technical Impact: total
CISA Coordinator (v2.0.3)
CWE
Assigner
References
7 references
| URL | Tags |
|---|---|
| https://developer.arm.com/documentation/112137 | |
| http://xenbits.xen.org/xsa/advisory-493.html | |
| http://www.openwall.com/lists/oss-security/2026/0… | |
| https://access.redhat.com/security/cve/CVE-2025-10263 | vdb-entryx_refsource_REDHAT |
| https://bugzilla.redhat.com/show_bug.cgi?id=2486958 | issue-trackingx_refsource_REDHAT |
| https://security.access.redhat.com/data/csaf/v2/v… | x_sadp-csaf-vex |
| https://access.redhat.com/errata/RHSA-2026:34911 | vendor-advisoryx_refsource_REDHAT |
Impacted products
32 products
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CVE-2025-0647 (GCVE-0-2025-0647)
Vulnerability from nvd – Published: 2026-01-14 10:58 – Updated: 2026-01-20 15:21
VLAI
Summary
In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the same PE or another PE in the shareability domain. In this case, the PE may retain stale TLB entries which should have been invalidated by the TLBI.
Severity
7.9 (High)
SSVC
Exploitation: none
Automatable: no
Technical Impact: total
CISA Coordinator (v2.0.3)
CWE
- CWE-226 - Sensitive Information in Resource Not Removed Before Reuse
Assigner
References
2 references
| URL | Tags |
|---|---|
| https://developer.arm.com/documentation/111546 | |
| https://graph.volerion.com/view?ID=CVE-2025-0647 | third-party-advisory |
Impacted products
11 products
| Vendor | Product | Version | |
|---|---|---|---|
| Arm | Neoverse-N2 |
Affected:
0
|
|
| Arm | Neoverse-V3AE |
Affected:
0
|
|
| Arm | Neoverse-V3 |
Affected:
0
|
|
| Arm | Neoverse-V2 |
Affected:
0
|
|
| Arm | Cortex-X925 |
Affected:
0
|
|
| Arm | Cortex-X4 |
Affected:
0
|
|
| Arm | Cortex-X3 |
Affected:
0
|
|
| Arm | Cortex-X2 |
Affected:
0
|
|
| Arm | Cortex-A710 |
Affected:
0
|
|
| Arm | C1-Premium |
Affected:
0
|
|
| Arm | C1-Ultra |
Affected:
0
|
Date Public
2026-01-14 10:48
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CVE-2024-5660 (GCVE-0-2024-5660)
Vulnerability from nvd – Published: 2024-12-10 13:55 – Updated: 2024-12-16 13:10
VLAI
Summary
Use of Hardware Page Aggregation (HPA) and Stage-1 and/or Stage-2 translation on Cortex-A77, Cortex-A78, Cortex-A78C, Cortex-A78AE, Cortex-A710, Cortex-X1, Cortex-X1C, Cortex-X2, Cortex-X3, Cortex-X4, Cortex-X925, Neoverse V1, Neoverse V2, Neoverse V3, Neoverse V3AE, Neoverse N2 may permit bypass of Stage-2 translation and/or GPT protection.
Severity
9.8 (Critical)
SSVC
Exploitation: none
Automatable: yes
Technical Impact: total
CISA Coordinator (v2.0.3)
CWE
- CWE-668 - Exposure of Resource to Wrong Sphere
Assigner
References
1 reference
Impacted products
16 products
| Vendor | Product | Version | |
|---|---|---|---|
| Arm | Cortex-A77 |
Affected:
0
(custom)
|
|
| Arm | Neoverse V1 |
Affected:
0
(custom)
|
|
| Arm | Cortex-A78AE |
Affected:
0
(custom)
|
|
| Arm | Cortex-78C |
Affected:
0
|
|
| Arm | Cortex-X1C |
Affected:
0
(custom)
|
|
| Arm | Cortex-A78 |
Affected:
0
(custom)
|
|
| Arm | Cortex-X1 |
Affected:
0
(custom)
|
|
| Arm | Neoverse N2 |
Affected:
0
(custom)
|
|
| Arm | Cortex-A710 |
Affected:
0
(custom)
|
|
| Arm | Cortex-X2 |
Affected:
0
(custom)
|
|
| Arm | Neoverse V2 |
Affected:
0
(custom)
|
|
| Arm | Cortex-X3 |
Affected:
0
(custom)
|
|
| Arm | Neoverse V3AE |
Affected:
0
(custom)
|
|
| Arm | Neoverse V3 |
Affected:
0
(custom)
|
|
| Arm | Cortex-X4 |
Affected:
0
(custom)
|
|
| Arm | Cortex-X925 |
Affected:
0
(custom)
|
Date Public
2024-12-10 13:54
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CVE-2025-10263 (GCVE-0-2025-10263)
Vulnerability from cvelistv5 – Published: 2026-06-09 09:23 – Updated: 2026-07-03 12:05
VLAI
Summary
Arm C1-Ultra, C1-Premium, Neoverse V3 & V3AE, Neoverse V2, Neoverse V1, Neoverse-N2, Neoverse-N1, Cortex-X925, Cortex-X4, Cortex-X3, Cortex-X2, Cortex-X1 & X1C, Cortex-A710, Cortex-A78, A78AE & A78C, Cortex-A77, Cortex-A76 & A76A may allow writes to resources owned by a higher exception level.
Severity
9.1 (Critical)
8.4 (High)
SSVC
Exploitation: none
Automatable: yes
Technical Impact: total
CISA Coordinator (v2.0.3)
CWE
Assigner
References
7 references
| URL | Tags |
|---|---|
| https://developer.arm.com/documentation/112137 | |
| http://xenbits.xen.org/xsa/advisory-493.html | |
| http://www.openwall.com/lists/oss-security/2026/0… | |
| https://access.redhat.com/security/cve/CVE-2025-10263 | vdb-entryx_refsource_REDHAT |
| https://bugzilla.redhat.com/show_bug.cgi?id=2486958 | issue-trackingx_refsource_REDHAT |
| https://security.access.redhat.com/data/csaf/v2/v… | x_sadp-csaf-vex |
| https://access.redhat.com/errata/RHSA-2026:34911 | vendor-advisoryx_refsource_REDHAT |
Impacted products
32 products
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CVE-2025-0647 (GCVE-0-2025-0647)
Vulnerability from cvelistv5 – Published: 2026-01-14 10:58 – Updated: 2026-01-20 15:21
VLAI
Summary
In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the same PE or another PE in the shareability domain. In this case, the PE may retain stale TLB entries which should have been invalidated by the TLBI.
Severity
7.9 (High)
SSVC
Exploitation: none
Automatable: no
Technical Impact: total
CISA Coordinator (v2.0.3)
CWE
- CWE-226 - Sensitive Information in Resource Not Removed Before Reuse
Assigner
References
2 references
| URL | Tags |
|---|---|
| https://developer.arm.com/documentation/111546 | |
| https://graph.volerion.com/view?ID=CVE-2025-0647 | third-party-advisory |
Impacted products
11 products
| Vendor | Product | Version | |
|---|---|---|---|
| Arm | Neoverse-N2 |
Affected:
0
|
|
| Arm | Neoverse-V3AE |
Affected:
0
|
|
| Arm | Neoverse-V3 |
Affected:
0
|
|
| Arm | Neoverse-V2 |
Affected:
0
|
|
| Arm | Cortex-X925 |
Affected:
0
|
|
| Arm | Cortex-X4 |
Affected:
0
|
|
| Arm | Cortex-X3 |
Affected:
0
|
|
| Arm | Cortex-X2 |
Affected:
0
|
|
| Arm | Cortex-A710 |
Affected:
0
|
|
| Arm | C1-Premium |
Affected:
0
|
|
| Arm | C1-Ultra |
Affected:
0
|
Date Public
2026-01-14 10:48
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CVE-2024-5660 (GCVE-0-2024-5660)
Vulnerability from cvelistv5 – Published: 2024-12-10 13:55 – Updated: 2024-12-16 13:10
VLAI
Summary
Use of Hardware Page Aggregation (HPA) and Stage-1 and/or Stage-2 translation on Cortex-A77, Cortex-A78, Cortex-A78C, Cortex-A78AE, Cortex-A710, Cortex-X1, Cortex-X1C, Cortex-X2, Cortex-X3, Cortex-X4, Cortex-X925, Neoverse V1, Neoverse V2, Neoverse V3, Neoverse V3AE, Neoverse N2 may permit bypass of Stage-2 translation and/or GPT protection.
Severity
9.8 (Critical)
SSVC
Exploitation: none
Automatable: yes
Technical Impact: total
CISA Coordinator (v2.0.3)
CWE
- CWE-668 - Exposure of Resource to Wrong Sphere
Assigner
References
1 reference
Impacted products
16 products
| Vendor | Product | Version | |
|---|---|---|---|
| Arm | Cortex-A77 |
Affected:
0
(custom)
|
|
| Arm | Neoverse V1 |
Affected:
0
(custom)
|
|
| Arm | Cortex-A78AE |
Affected:
0
(custom)
|
|
| Arm | Cortex-78C |
Affected:
0
|
|
| Arm | Cortex-X1C |
Affected:
0
(custom)
|
|
| Arm | Cortex-A78 |
Affected:
0
(custom)
|
|
| Arm | Cortex-X1 |
Affected:
0
(custom)
|
|
| Arm | Neoverse N2 |
Affected:
0
(custom)
|
|
| Arm | Cortex-A710 |
Affected:
0
(custom)
|
|
| Arm | Cortex-X2 |
Affected:
0
(custom)
|
|
| Arm | Neoverse V2 |
Affected:
0
(custom)
|
|
| Arm | Cortex-X3 |
Affected:
0
(custom)
|
|
| Arm | Neoverse V3AE |
Affected:
0
(custom)
|
|
| Arm | Neoverse V3 |
Affected:
0
(custom)
|
|
| Arm | Cortex-X4 |
Affected:
0
(custom)
|
|
| Arm | Cortex-X925 |
Affected:
0
(custom)
|
Date Public
2024-12-10 13:54
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