Common Weakness Enumeration

CWE-1252

Weakness Allowed

CPU Hardware Not Configured to Support Exclusivity of Write and Execute Operations

Abstraction: Base · Status: Incomplete

The CPU is not configured to provide hardware support for exclusivity of write and execute operations on memory. This allows an attacker to execute data from all of memory.

Mapping guidance

This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.

Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.

Relationships and members
ChildOf: CWE-284 · View CWE-1000
Modes of introduction
Architecture and Design

If the CPU does not have an MMU/MPU, then there is no write exclusivity.

Content history
Submission: Arun Kanuparthi, Hareesh Khattri, Parbati Kumar Manna, Narasimha Kumar V Mangipudi · Intel Corporation · 2020-02-13 · CWE 4.0
Modification: CWE Content Team · MITRE · 2020-08-20 · CWE 4.2

updated Related_Attack_Patterns

Modification: CWE Content Team · MITRE · 2022-04-28 · CWE 4.7

updated Applicable_Platforms, Related_Attack_Patterns

Modification: CWE Content Team · MITRE · 2022-06-28 · CWE 4.8

updated Applicable_Platforms

Modification: CWE Content Team · MITRE · 2023-04-27 · CWE 4.11

updated References, Relationships

Modification: CWE Content Team · MITRE · 2023-06-29 · CWE 4.12

updated Mapping_Notes

Modification: CWE Content Team · MITRE · 2025-12-11 · CWE 4.19

updated Common_Consequences, Description, Weakness_Ordinalities

Modification: CWE Content Team · MITRE · 2026-10-28 · CWE 5.0

updated Background_Details, Description, Modes_of_Introduction

0 vulnerabilities reference this CWE, most recent first.

No vulnerabilities reference this CWE.

Mitigation
Architecture and Design

Implement a dedicated bit that can be leveraged by the Operating System to mark data areas as non-executable. If such a bit is not available in the CPU, implement MMU/MPU (memory management unit / memory protection unit).

Mitigation
Integration

If MMU/MPU are not available, then the firewalls need to be implemented in the SoC interconnect to mimic the write-exclusivity operation.

CAPEC-679: Exploitation of Improperly Configured or Implemented Memory Protections

An adversary takes advantage of missing or incorrectly configured access control within memory to read/write data or inject malicious code into said memory.