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4 vulnerabilities by chipsalliance
CVE-2025-63384 (GCVE-0-2025-63384)
Vulnerability from nvd – Published: 2025-11-10 00:00 – Updated: 2025-11-12 20:39
VLAI
Summary
A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exception Return) instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode (M-mode) to Supervisor-mode (S-mode) as specified by the sstatus.SPP bit, the processor incorrectly remains in M-mode, leading to a critical privilege retention vulnerability.
Severity
6.5 (Medium)
SSVC
Exploitation: none
Automatable: no
Technical Impact: total
CISA Coordinator (v2.0.3)
CWE
- n/a
- CWE-266 - Incorrect Privilege Assignment
Assigner
References
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"confidentialityImpact": "HIGH",
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CVE-2025-56301 (GCVE-0-2025-56301)
Vulnerability from nvd – Published: 2025-09-30 00:00 – Updated: 2025-10-01 19:53
VLAI
Summary
An issue was discovered in Chipsalliance Rocket-Chip commit f517abbf41abb65cea37421d3559f9739efd00a9 (2025-01-29) allowing attackers to corrupt exception handling and privilege state transitions via a flawed interaction between exception handling and MRET return mechanisms in the CSR logic when an exception is triggered during MRET execution. The Control and Status Register (CSR) logic has a flawed interaction between exception handling and exception return (MRET) mechanisms which can cause faulty trap behavior. When the MRET instruction is executed in machine mode without being in an exception state, an Instruction Access Fault may be triggered. This results in both the exception handling logic and the exception return logic activating simultaneously, leading to conflicting updates to the control and status registers.
Severity
7.5 (High)
SSVC
Exploitation: none
Automatable: no
Technical Impact: partial
CISA Coordinator (v2.0.3)
CWE
- n/a
- CWE-1281 - Sequence of Processor Instructions Leads to Unexpected Behavior
Assigner
References
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"integrityImpact": "NONE",
"privilegesRequired": "NONE",
"scope": "UNCHANGED",
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}
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"references": [
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"url": "https://github.com/chipsalliance/rocket-chip"
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"url": "https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/rocket/CSR.scala"
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CVE-2025-63384 (GCVE-0-2025-63384)
Vulnerability from cvelistv5 – Published: 2025-11-10 00:00 – Updated: 2025-11-12 20:39
VLAI
Summary
A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exception Return) instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode (M-mode) to Supervisor-mode (S-mode) as specified by the sstatus.SPP bit, the processor incorrectly remains in M-mode, leading to a critical privilege retention vulnerability.
Severity
6.5 (Medium)
SSVC
Exploitation: none
Automatable: no
Technical Impact: total
CISA Coordinator (v2.0.3)
CWE
- n/a
- CWE-266 - Incorrect Privilege Assignment
Assigner
References
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"confidentialityImpact": "HIGH",
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CVE-2025-56301 (GCVE-0-2025-56301)
Vulnerability from cvelistv5 – Published: 2025-09-30 00:00 – Updated: 2025-10-01 19:53
VLAI
Summary
An issue was discovered in Chipsalliance Rocket-Chip commit f517abbf41abb65cea37421d3559f9739efd00a9 (2025-01-29) allowing attackers to corrupt exception handling and privilege state transitions via a flawed interaction between exception handling and MRET return mechanisms in the CSR logic when an exception is triggered during MRET execution. The Control and Status Register (CSR) logic has a flawed interaction between exception handling and exception return (MRET) mechanisms which can cause faulty trap behavior. When the MRET instruction is executed in machine mode without being in an exception state, an Instruction Access Fault may be triggered. This results in both the exception handling logic and the exception return logic activating simultaneously, leading to conflicting updates to the control and status registers.
Severity
7.5 (High)
SSVC
Exploitation: none
Automatable: no
Technical Impact: partial
CISA Coordinator (v2.0.3)
CWE
- n/a
- CWE-1281 - Sequence of Processor Instructions Leads to Unexpected Behavior
Assigner
References
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"integrityImpact": "NONE",
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