CVE-2024-26670 (GCVE-0-2024-26670)

Vulnerability from cvelistv5 – Published: 2024-04-02 06:43 – Updated: 2026-05-23 15:36
VLAI
Title
arm64: entry: fix ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD
Summary
In the Linux kernel, the following vulnerability has been resolved: arm64: entry: fix ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD Currently the ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD workaround isn't quite right, as it is supposed to be applied after the last explicit memory access, but is immediately followed by an LDR. The ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD workaround is used to handle Cortex-A520 erratum 2966298 and Cortex-A510 erratum 3117295, which are described in: * https://developer.arm.com/documentation/SDEN2444153/0600/?lang=en * https://developer.arm.com/documentation/SDEN1873361/1600/?lang=en In both cases the workaround is described as: | If pagetable isolation is disabled, the context switch logic in the | kernel can be updated to execute the following sequence on affected | cores before exiting to EL0, and after all explicit memory accesses: | | 1. A non-shareable TLBI to any context and/or address, including | unused contexts or addresses, such as a `TLBI VALE1 Xzr`. | | 2. A DSB NSH to guarantee completion of the TLBI. The important part being that the TLBI+DSB must be placed "after all explicit memory accesses". Unfortunately, as-implemented, the TLBI+DSB is immediately followed by an LDR, as we have: | alternative_if ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD | tlbi vale1, xzr | dsb nsh | alternative_else_nop_endif | alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0 | ldr lr, [sp, #S_LR] | add sp, sp, #PT_REGS_SIZE // restore sp | eret | alternative_else_nop_endif | | [ ... KPTI exception return path ... ] This patch fixes this by reworking the logic to place the TLBI+DSB immediately before the ERET, after all explicit memory accesses. The ERET is currently in a separate alternative block, and alternatives cannot be nested. To account for this, the alternative block for ARM64_UNMAP_KERNEL_AT_EL0 is replaced with a single alternative branch to skip the KPTI logic, with the new shape of the logic being: | alternative_insn "b .L_skip_tramp_exit_\@", nop, ARM64_UNMAP_KERNEL_AT_EL0 | [ ... KPTI exception return path ... ] | .L_skip_tramp_exit_\@: | | ldr lr, [sp, #S_LR] | add sp, sp, #PT_REGS_SIZE // restore sp | | alternative_if ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD | tlbi vale1, xzr | dsb nsh | alternative_else_nop_endif | eret The new structure means that the workaround is only applied when KPTI is not in use; this is fine as noted in the documented implications of the erratum: | Pagetable isolation between EL0 and higher level ELs prevents the | issue from occurring. ... and as per the workaround description quoted above, the workaround is only necessary "If pagetable isolation is disabled".
Severity
5.5 (Medium)
CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:N/I:N/A:H
SSVC
Exploitation: none Automatable: no Technical Impact: partial
CISA Coordinator (v2.0.3)
CWE
Assigner
References
Impacted products
Vendor Product Version
Linux Linux Affected: 471470bc7052d28ce125901877dd10e4c048e513 , < 58eb5c07f41704464b9acc09ab0707b6769db6c0 (git)
Affected: 471470bc7052d28ce125901877dd10e4c048e513 , < baa0aaac16432019651e0d60c41cd34a0c3c3477 (git)
Affected: 471470bc7052d28ce125901877dd10e4c048e513 , < 832dd634bd1b4e3bbe9f10b9c9ba5db6f6f2b97f (git)
Affected: 6e3ae2927b432a3b7c8374f14dbc1bd9ebe4372c (git)
Affected: 32b0a4ffcaea44a00a61e40c0d1bcc50362aee25 (git)
Affected: 6.1.57 , < 6.2 (semver)
Affected: 6.5.7 , < 6.6 (semver)
Create a notification for this product.
Linux Linux Affected: 6.6
Unaffected: 0 , < 6.6 (semver)
Unaffected: 6.6.15 , ≤ 6.6.* (semver)
Unaffected: 6.7.3 , ≤ 6.7.* (semver)
Unaffected: 6.8 , ≤ * (original_commit_for_fix)
Create a notification for this product.
Show details on NVD website
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      "descriptions": "[{\"lang\": \"en\", \"value\": \"In the Linux kernel, the following vulnerability has been resolved:\\n\\narm64: entry: fix ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD\\n\\nCurrently the ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD workaround isn\u0027t\\nquite right, as it is supposed to be applied after the last explicit\\nmemory access, but is immediately followed by an LDR.\\n\\nThe ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD workaround is used to\\nhandle Cortex-A520 erratum 2966298 and Cortex-A510 erratum 3117295,\\nwhich are described in:\\n\\n* https://developer.arm.com/documentation/SDEN2444153/0600/?lang=en\\n* https://developer.arm.com/documentation/SDEN1873361/1600/?lang=en\\n\\nIn both cases the workaround is described as:\\n\\n| If pagetable isolation is disabled, the context switch logic in the\\n| kernel can be updated to execute the following sequence on affected\\n| cores before exiting to EL0, and after all explicit memory accesses:\\n|\\n| 1. A non-shareable TLBI to any context and/or address, including\\n|    unused contexts or addresses, such as a `TLBI VALE1 Xzr`.\\n|\\n| 2. A DSB NSH to guarantee completion of the TLBI.\\n\\nThe important part being that the TLBI+DSB must be placed \\\"after all\\nexplicit memory accesses\\\".\\n\\nUnfortunately, as-implemented, the TLBI+DSB is immediately followed by\\nan LDR, as we have:\\n\\n| alternative_if ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD\\n| \\ttlbi\\tvale1, xzr\\n| \\tdsb\\tnsh\\n| alternative_else_nop_endif\\n| alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0\\n| \\tldr\\tlr, [sp, #S_LR]\\n| \\tadd\\tsp, sp, #PT_REGS_SIZE\\t\\t// restore sp\\n| \\teret\\n| alternative_else_nop_endif\\n|\\n| [ ... KPTI exception return path ... ]\\n\\nThis patch fixes this by reworking the logic to place the TLBI+DSB\\nimmediately before the ERET, after all explicit memory accesses.\\n\\nThe ERET is currently in a separate alternative block, and alternatives\\ncannot be nested. To account for this, the alternative block for\\nARM64_UNMAP_KERNEL_AT_EL0 is replaced with a single alternative branch\\nto skip the KPTI logic, with the new shape of the logic being:\\n\\n| alternative_insn \\\"b .L_skip_tramp_exit_\\\\@\\\", nop, ARM64_UNMAP_KERNEL_AT_EL0\\n| \\t[ ... KPTI exception return path ... ]\\n| .L_skip_tramp_exit_\\\\@:\\n|\\n| \\tldr\\tlr, [sp, #S_LR]\\n| \\tadd\\tsp, sp, #PT_REGS_SIZE\\t\\t// restore sp\\n|\\n| alternative_if ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD\\n| \\ttlbi\\tvale1, xzr\\n| \\tdsb\\tnsh\\n| alternative_else_nop_endif\\n| \\teret\\n\\nThe new structure means that the workaround is only applied when KPTI is\\nnot in use; this is fine as noted in the documented implications of the\\nerratum:\\n\\n| Pagetable isolation between EL0 and higher level ELs prevents the\\n| issue from occurring.\\n\\n... and as per the workaround description quoted above, the workaround\\nis only necessary \\\"If pagetable isolation is disabled\\\".\"}, {\"lang\": \"es\", \"value\": \"En el kernel de Linux, se ha resuelto la siguiente vulnerabilidad: arm64: entrada: arreglar ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD Actualmente, la soluci\\u00f3n alternativa ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD no es del todo correcta, ya que se supone que debe aplicarse despu\\u00e9s del \\u00faltimo acceso expl\\u00edcito a la memoria, pero va seguida inmediatamente por un LDR. La soluci\\u00f3n alternativa ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD se utiliza para manejar las erratas Cortex-A520 2966298 y Cortex-A510 erratas 3117295, que se describen en: * https://developer.arm.com/documentation/SDEN2444153/0600/?lang=en * https:// desarrollador.arm.com/documentation/SDEN1873361/1600/?lang=en En ambos casos, la soluci\\u00f3n se describe como: | Si el aislamiento de la tabla de p\\u00e1ginas est\\u00e1 deshabilitado, la l\\u00f3gica de cambio de contexto en | El kernel se puede actualizar para ejecutar la siguiente secuencia en los afectados | n\\u00facleos antes de salir a EL0 y despu\\u00e9s de todos los accesos expl\\u00edcitos a la memoria: | | 1. Un TLBI que no se puede compartir en cualquier contexto y/o direcci\\u00f3n, incluido | contextos o direcciones no utilizados, como `TLBI VALE1 Xzr`. | | 2. Un OSD NSH para garantizar la finalizaci\\u00f3n del TLBI. La parte importante es que el TLBI+DSB debe colocarse \\\"despu\\u00e9s de todos los accesos expl\\u00edcitos a la memoria\\\". Desafortunadamente, tal como se implement\\u00f3, el TLBI+DSB es seguido inmediatamente por un LDR, como tenemos: | Alternative_if ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD | tlbi vale1, xzr | dsb nsh | alternativa_else_nop_endif | alternativa_si_no ARM64_UNMAP_KERNEL_AT_EL0 | ldr lr, [sp, #S_LR] | agregar sp, sp, #PT_REGS_SIZE // restaurar sp | eremita | alternativa_else_nop_endif | | [... Ruta de retorno de excepci\\u00f3n KPTI...] Este parche soluciona este problema reelaborando la l\\u00f3gica para colocar TLBI+DSB inmediatamente antes de ERET, despu\\u00e9s de todos los accesos expl\\u00edcitos a la memoria. El ERET se encuentra actualmente en un bloque alternativo separado y las alternativas no se pueden anidar. Para tener en cuenta esto, el bloque alternativo para ARM64_UNMAP_KERNEL_AT_EL0 se reemplaza con una \\u00fanica rama alternativa para omitir la l\\u00f3gica KPTI, siendo la nueva forma de la l\\u00f3gica: | Alternative_insn \\\"b .L_skip_tramp_exit_\\\\@\\\", nop, ARM64_UNMAP_KERNEL_AT_EL0 | [... Ruta de retorno de excepci\\u00f3n KPTI...] | .L_skip_tramp_exit_\\\\@: | | ldr lr, [sp, #S_LR] | agregar sp, sp, #PT_REGS_SIZE // restaurar sp | | Alternative_if ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD | tlbi vale1, xzr | dsb nsh | alternativa_else_nop_endif | eret La nueva estructura significa que la soluci\\u00f3n alternativa s\\u00f3lo se aplica cuando KPTI no est\\u00e1 en uso; esto est\\u00e1 bien, como se indica en las implicaciones documentadas de la fe de erratas: | El aislamiento de la tabla de paginaci\\u00f3n entre EL0 y los EL de nivel superior evita que | que ocurra el problema. ... y seg\\u00fan la descripci\\u00f3n de la soluci\\u00f3n citada anteriormente, la soluci\\u00f3n s\\u00f3lo es necesaria \\\"si el aislamiento de la tabla de p\\u00e1ginas est\\u00e1 deshabilitado\\\".\"}]",
      "id": "CVE-2024-26670",
      "lastModified": "2024-11-21T09:02:48.597",
      "published": "2024-04-02T07:15:43.760",
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      "vulnStatus": "Awaiting Analysis"
    },
    "nvd": "{\"cve\":{\"id\":\"CVE-2024-26670\",\"sourceIdentifier\":\"416baaa9-dc9f-4396-8d5f-8c081fb06d67\",\"published\":\"2024-04-02T07:15:43.760\",\"lastModified\":\"2025-10-01T18:15:36.873\",\"vulnStatus\":\"Modified\",\"cveTags\":[],\"descriptions\":[{\"lang\":\"en\",\"value\":\"In the Linux kernel, the following vulnerability has been resolved:\\n\\narm64: entry: fix ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD\\n\\nCurrently the ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD workaround isn\u0027t\\nquite right, as it is supposed to be applied after the last explicit\\nmemory access, but is immediately followed by an LDR.\\n\\nThe ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD workaround is used to\\nhandle Cortex-A520 erratum 2966298 and Cortex-A510 erratum 3117295,\\nwhich are described in:\\n\\n* https://developer.arm.com/documentation/SDEN2444153/0600/?lang=en\\n* https://developer.arm.com/documentation/SDEN1873361/1600/?lang=en\\n\\nIn both cases the workaround is described as:\\n\\n| If pagetable isolation is disabled, the context switch logic in the\\n| kernel can be updated to execute the following sequence on affected\\n| cores before exiting to EL0, and after all explicit memory accesses:\\n|\\n| 1. A non-shareable TLBI to any context and/or address, including\\n|    unused contexts or addresses, such as a `TLBI VALE1 Xzr`.\\n|\\n| 2. A DSB NSH to guarantee completion of the TLBI.\\n\\nThe important part being that the TLBI+DSB must be placed \\\"after all\\nexplicit memory accesses\\\".\\n\\nUnfortunately, as-implemented, the TLBI+DSB is immediately followed by\\nan LDR, as we have:\\n\\n| alternative_if ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD\\n| \\ttlbi\\tvale1, xzr\\n| \\tdsb\\tnsh\\n| alternative_else_nop_endif\\n| alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0\\n| \\tldr\\tlr, [sp, #S_LR]\\n| \\tadd\\tsp, sp, #PT_REGS_SIZE\\t\\t// restore sp\\n| \\teret\\n| alternative_else_nop_endif\\n|\\n| [ ... KPTI exception return path ... ]\\n\\nThis patch fixes this by reworking the logic to place the TLBI+DSB\\nimmediately before the ERET, after all explicit memory accesses.\\n\\nThe ERET is currently in a separate alternative block, and alternatives\\ncannot be nested. To account for this, the alternative block for\\nARM64_UNMAP_KERNEL_AT_EL0 is replaced with a single alternative branch\\nto skip the KPTI logic, with the new shape of the logic being:\\n\\n| alternative_insn \\\"b .L_skip_tramp_exit_\\\\@\\\", nop, ARM64_UNMAP_KERNEL_AT_EL0\\n| \\t[ ... KPTI exception return path ... ]\\n| .L_skip_tramp_exit_\\\\@:\\n|\\n| \\tldr\\tlr, [sp, #S_LR]\\n| \\tadd\\tsp, sp, #PT_REGS_SIZE\\t\\t// restore sp\\n|\\n| alternative_if ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD\\n| \\ttlbi\\tvale1, xzr\\n| \\tdsb\\tnsh\\n| alternative_else_nop_endif\\n| \\teret\\n\\nThe new structure means that the workaround is only applied when KPTI is\\nnot in use; this is fine as noted in the documented implications of the\\nerratum:\\n\\n| Pagetable isolation between EL0 and higher level ELs prevents the\\n| issue from occurring.\\n\\n... and as per the workaround description quoted above, the workaround\\nis only necessary \\\"If pagetable isolation is disabled\\\".\"},{\"lang\":\"es\",\"value\":\"En el kernel de Linux, se ha resuelto la siguiente vulnerabilidad: arm64: entrada: arreglar ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD Actualmente, la soluci\u00f3n alternativa ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD no es del todo correcta, ya que se supone que debe aplicarse despu\u00e9s del \u00faltimo acceso expl\u00edcito a la memoria, pero va seguida inmediatamente por un LDR. La soluci\u00f3n alternativa ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD se utiliza para manejar las erratas Cortex-A520 2966298 y Cortex-A510 erratas 3117295, que se describen en: * https://developer.arm.com/documentation/SDEN2444153/0600/?lang=en * https:// desarrollador.arm.com/documentation/SDEN1873361/1600/?lang=en En ambos casos, la soluci\u00f3n se describe como: | Si el aislamiento de la tabla de p\u00e1ginas est\u00e1 deshabilitado, la l\u00f3gica de cambio de contexto en | El kernel se puede actualizar para ejecutar la siguiente secuencia en los afectados | n\u00facleos antes de salir a EL0 y despu\u00e9s de todos los accesos expl\u00edcitos a la memoria: | | 1. Un TLBI que no se puede compartir en cualquier contexto y/o direcci\u00f3n, incluido | contextos o direcciones no utilizados, como `TLBI VALE1 Xzr`. | | 2. Un OSD NSH para garantizar la finalizaci\u00f3n del TLBI. La parte importante es que el TLBI+DSB debe colocarse \\\"despu\u00e9s de todos los accesos expl\u00edcitos a la memoria\\\". Desafortunadamente, tal como se implement\u00f3, el TLBI+DSB es seguido inmediatamente por un LDR, como tenemos: | Alternative_if ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD | tlbi vale1, xzr | dsb nsh | alternativa_else_nop_endif | alternativa_si_no ARM64_UNMAP_KERNEL_AT_EL0 | ldr lr, [sp, #S_LR] | agregar sp, sp, #PT_REGS_SIZE // restaurar sp | eremita | alternativa_else_nop_endif | | [... Ruta de retorno de excepci\u00f3n KPTI...] Este parche soluciona este problema reelaborando la l\u00f3gica para colocar TLBI+DSB inmediatamente antes de ERET, despu\u00e9s de todos los accesos expl\u00edcitos a la memoria. El ERET se encuentra actualmente en un bloque alternativo separado y las alternativas no se pueden anidar. Para tener en cuenta esto, el bloque alternativo para ARM64_UNMAP_KERNEL_AT_EL0 se reemplaza con una \u00fanica rama alternativa para omitir la l\u00f3gica KPTI, siendo la nueva forma de la l\u00f3gica: | Alternative_insn \\\"b .L_skip_tramp_exit_\\\\@\\\", nop, ARM64_UNMAP_KERNEL_AT_EL0 | [... Ruta de retorno de excepci\u00f3n KPTI...] | .L_skip_tramp_exit_\\\\@: | | ldr lr, [sp, #S_LR] | agregar sp, sp, #PT_REGS_SIZE // restaurar sp | | Alternative_if ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD | tlbi vale1, xzr | dsb nsh | alternativa_else_nop_endif | eret La nueva estructura significa que la soluci\u00f3n alternativa s\u00f3lo se aplica cuando KPTI no est\u00e1 en uso; esto est\u00e1 bien, como se indica en las implicaciones documentadas de la fe de erratas: | El aislamiento de la tabla de paginaci\u00f3n entre EL0 y los EL de nivel superior evita que | que ocurra el problema. ... y seg\u00fan la descripci\u00f3n de la soluci\u00f3n citada anteriormente, la soluci\u00f3n s\u00f3lo es necesaria \\\"si el aislamiento de la tabla de p\u00e1ginas est\u00e1 deshabilitado\\\".\"}],\"metrics\":{\"cvssMetricV31\":[{\"source\":\"nvd@nist.gov\",\"type\":\"Primary\",\"cvssData\":{\"version\":\"3.1\",\"vectorString\":\"CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:N/I:N/A:H\",\"baseScore\":5.5,\"baseSeverity\":\"MEDIUM\",\"attackVector\":\"LOCAL\",\"attackComplexity\":\"LOW\",\"privilegesRequired\":\"LOW\",\"userInteraction\":\"NONE\",\"scope\":\"UNCHANGED\",\"confidentialityImpact\":\"NONE\",\"integrityImpact\":\"NONE\",\"availabilityImpact\":\"HIGH\"},\"exploitabilityScore\":1.8,\"impactScore\":3.6},{\"source\":\"134c704f-9b21-4f2e-91b3-4a467353bcc0\",\"type\":\"Secondary\",\"cvssData\":{\"version\":\"3.1\",\"vectorString\":\"CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:N/I:N/A:H\",\"baseScore\":5.5,\"baseSeverity\":\"MEDIUM\",\"attackVector\":\"LOCAL\",\"attackComplexity\":\"LOW\",\"privilegesRequired\":\"LOW\",\"userInteraction\":\"NONE\",\"scope\":\"UNCHANGED\",\"confidentialityImpact\":\"NONE\",\"integrityImpact\":\"NONE\",\"availabilityImpact\":\"HIGH\"},\"exploitabilityScore\":1.8,\"impactScore\":3.6}]},\"weaknesses\":[{\"source\":\"nvd@nist.gov\",\"type\":\"Primary\",\"description\":[{\"lang\":\"en\",\"value\":\"CWE-787\"}]},{\"source\":\"134c704f-9b21-4f2e-91b3-4a467353bcc0\",\"type\":\"Secondary\",\"description\":[{\"lang\":\"en\",\"value\":\"CWE-787\"}]}],\"configurations\":[{\"nodes\":[{\"operator\":\"OR\",\"negate\":false,\"cpeMatch\":[{\"vulnerable\":true,\"criteria\":\"cpe:2.3:o:linux:linux_kernel:*:*:*:*:*:*:*:*\",\"versionStartIncluding\":\"6.6\",\"versionEndExcluding\":\"6.6.15\",\"matchCriteriaId\":\"EB070897-9C4B-4820-AE94-31318C9F5D76\"},{\"vulnerable\":true,\"criteria\":\"cpe:2.3:o:linux:linux_kernel:*:*:*:*:*:*:*:*\",\"versionStartIncluding\":\"6.7\",\"versionEndExcluding\":\"6.7.3\",\"matchCriteriaId\":\"58FD5308-148A-40D3-B36A-0CA6B434A8BF\"}]}]}],\"references\":[{\"url\":\"https://git.kernel.org/stable/c/58eb5c07f41704464b9acc09ab0707b6769db6c0\",\"source\":\"416baaa9-dc9f-4396-8d5f-8c081fb06d67\",\"tags\":[\"Patch\"]},{\"url\":\"https://git.kernel.org/stable/c/832dd634bd1b4e3bbe9f10b9c9ba5db6f6f2b97f\",\"source\":\"416baaa9-dc9f-4396-8d5f-8c081fb06d67\",\"tags\":[\"Patch\"]},{\"url\":\"https://git.kernel.org/stable/c/baa0aaac16432019651e0d60c41cd34a0c3c3477\",\"source\":\"416baaa9-dc9f-4396-8d5f-8c081fb06d67\",\"tags\":[\"Patch\"]},{\"url\":\"https://git.kernel.org/stable/c/58eb5c07f41704464b9acc09ab0707b6769db6c0\",\"source\":\"af854a3a-2127-422b-91ae-364da2661108\",\"tags\":[\"Patch\"]},{\"url\":\"https://git.kernel.org/stable/c/832dd634bd1b4e3bbe9f10b9c9ba5db6f6f2b97f\",\"source\":\"af854a3a-2127-422b-91ae-364da2661108\",\"tags\":[\"Patch\"]},{\"url\":\"https://git.kernel.org/stable/c/baa0aaac16432019651e0d60c41cd34a0c3c3477\",\"source\":\"af854a3a-2127-422b-91ae-364da2661108\",\"tags\":[\"Patch\"]}]}}",
    "vulnrichment": {
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A non-shareable TLBI to any context and/or address, including\\n|    unused contexts or addresses, such as a `TLBI VALE1 Xzr`.\\n|\\n| 2. A DSB NSH to guarantee completion of the TLBI.\\n\\nThe important part being that the TLBI+DSB must be placed \\\"after all\\nexplicit memory accesses\\\".\\n\\nUnfortunately, as-implemented, the TLBI+DSB is immediately followed by\\nan LDR, as we have:\\n\\n| alternative_if ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD\\n| \\ttlbi\\tvale1, xzr\\n| \\tdsb\\tnsh\\n| alternative_else_nop_endif\\n| alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0\\n| \\tldr\\tlr, [sp, #S_LR]\\n| \\tadd\\tsp, sp, #PT_REGS_SIZE\\t\\t// restore sp\\n| \\teret\\n| alternative_else_nop_endif\\n|\\n| [ ... KPTI exception return path ... ]\\n\\nThis patch fixes this by reworking the logic to place the TLBI+DSB\\nimmediately before the ERET, after all explicit memory accesses.\\n\\nThe ERET is currently in a separate alternative block, and alternatives\\ncannot be nested. To account for this, the alternative block for\\nARM64_UNMAP_KERNEL_AT_EL0 is replaced with a single alternative branch\\nto skip the KPTI logic, with the new shape of the logic being:\\n\\n| alternative_insn \\\"b .L_skip_tramp_exit_\\\\@\\\", nop, ARM64_UNMAP_KERNEL_AT_EL0\\n| \\t[ ... KPTI exception return path ... ]\\n| .L_skip_tramp_exit_\\\\@:\\n|\\n| \\tldr\\tlr, [sp, #S_LR]\\n| \\tadd\\tsp, sp, #PT_REGS_SIZE\\t\\t// restore sp\\n|\\n| alternative_if ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD\\n| \\ttlbi\\tvale1, xzr\\n| \\tdsb\\tnsh\\n| alternative_else_nop_endif\\n| \\teret\\n\\nThe new structure means that the workaround is only applied when KPTI is\\nnot in use; this is fine as noted in the documented implications of the\\nerratum:\\n\\n| Pagetable isolation between EL0 and higher level ELs prevents the\\n| issue from occurring.\\n\\n... and as per the workaround description quoted above, the workaround\\nis only necessary \\\"If pagetable isolation is disabled\\\".\"}], \"cpeApplicability\": [{\"nodes\": [{\"negate\": false, \"cpeMatch\": [{\"criteria\": \"cpe:2.3:o:linux:linux_kernel:*:*:*:*:*:*:*:*\", \"vulnerable\": true, \"versionEndExcluding\": \"6.6.15\", \"versionStartIncluding\": \"6.6\"}, {\"criteria\": \"cpe:2.3:o:linux:linux_kernel:*:*:*:*:*:*:*:*\", \"vulnerable\": true, \"versionEndExcluding\": \"6.7.3\", \"versionStartIncluding\": \"6.6\"}, {\"criteria\": \"cpe:2.3:o:linux:linux_kernel:*:*:*:*:*:*:*:*\", \"vulnerable\": true, \"versionEndExcluding\": \"6.8\", \"versionStartIncluding\": \"6.6\"}, {\"criteria\": \"cpe:2.3:o:linux:linux_kernel:*:*:*:*:*:*:*:*\", \"vulnerable\": true, \"versionStartIncluding\": \"6.1.57\"}, {\"criteria\": \"cpe:2.3:o:linux:linux_kernel:*:*:*:*:*:*:*:*\", \"vulnerable\": true, \"versionStartIncluding\": \"6.5.7\"}], \"operator\": \"OR\"}]}], \"providerMetadata\": {\"orgId\": \"416baaa9-dc9f-4396-8d5f-8c081fb06d67\", \"shortName\": \"Linux\", \"dateUpdated\": \"2026-05-11T20:01:55.161Z\"}}}",
      "cveMetadata": "{\"cveId\": \"CVE-2024-26670\", \"state\": \"PUBLISHED\", \"dateUpdated\": \"2026-05-11T20:01:55.161Z\", \"dateReserved\": \"2024-02-19T14:20:24.150Z\", \"assignerOrgId\": \"416baaa9-dc9f-4396-8d5f-8c081fb06d67\", \"datePublished\": \"2024-04-02T06:43:31.201Z\", \"assignerShortName\": \"Linux\"}",
      "dataType": "CVE_RECORD",
      "dataVersion": "5.2"
    }
  }
}


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Forecast uses a logistic model when the trend is rising, or an exponential decay model when the trend is falling. Fitted via linearized least squares.

Sightings

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Nomenclature

  • Seen: The vulnerability was mentioned, discussed, or observed by the user.
  • Confirmed: The vulnerability has been validated from an analyst's perspective.
  • Published Proof of Concept: A public proof of concept is available for this vulnerability.
  • Exploited: The vulnerability was observed as exploited by the user who reported the sighting.
  • Patched: The vulnerability was observed as successfully patched by the user who reported the sighting.
  • Not exploited: The vulnerability was not observed as exploited by the user who reported the sighting.
  • Not confirmed: The user expressed doubt about the validity of the vulnerability.
  • Not patched: The vulnerability was not observed as successfully patched by the user who reported the sighting.


Detection rules are retrieved from Rulezet.