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        "url": "https://www.first.org/tlp/"
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      {
        "category": "summary",
        "text": "An update for rhvm-setup-plugins is now available for Red Hat Virtualization 4.2.\n\nRed Hat Product Security has rated this update as having a security impact of Important. A Common Vulnerability Scoring System (CVSS) base score, which gives a detailed severity rating, is available for each vulnerability from the CVE link(s) in the References section.",
        "title": "Topic"
      },
      {
        "category": "general",
        "text": "The rhvm-setup-plugins package adds functionality exclusive only to Red Hat Virtualization Manager, and is not available for the upstream ovirt-engine. It includes the configuration of the Red Hat Support plugin, copying downstream-only artifacts to the ISO domain, and links to the knowledgebase and other support material.\n\nSecurity Fix(es):\n\n* A flaw was found in the implementation of the \"fill buffer\", a mechanism used by modern CPUs when a cache-miss is made on L1 CPU cache. If an attacker can generate a load operation that would create a page fault, the execution will continue speculatively with incorrect data from the fill buffer while the data is fetched from higher level caches. This response time can be measured to infer data in the fill buffer. (CVE-2018-12130)\n\n* Modern Intel microprocessors implement hardware-level micro-optimizations to improve the performance of writing data back to CPU caches. The write operation is split into STA (STore Address) and STD (STore Data) sub-operations. These sub-operations allow the processor to hand-off address generation logic into these sub-operations for optimized writes. Both of these sub-operations write to a shared distributed processor structure called the \u0027processor store buffer\u0027. As a result, an unprivileged attacker could use this flaw to read private data resident within the CPU\u0027s processor store buffer. (CVE-2018-12126)\n\n* Microprocessors use a \u2018load port\u2019 subcomponent to perform load operations from memory or IO. During a load operation, the load port receives data from the memory or IO subsystem and then provides the data to the CPU registers and operations in the CPU\u2019s pipelines. Stale load operations results are stored in the \u0027load port\u0027 table until overwritten by newer operations. Certain load-port operations triggered by an attacker can be used to reveal data about previous stale requests leaking data back to the attacker via a timing side-channel. (CVE-2018-12127)\n\n* Uncacheable memory on some microprocessors utilizing speculative execution may allow an authenticated user to potentially enable information disclosure via a side channel with local access. (CVE-2019-11091)\n\nFor more details about the security issue(s), including the impact, a CVSS score, acknowledgments, and other related information, refer to the CVE page(s) listed in the References section.",
        "title": "Details"
      },
      {
        "category": "legal_disclaimer",
        "text": "This content is licensed under the Creative Commons Attribution 4.0 International License (https://creativecommons.org/licenses/by/4.0/). If you distribute this content, or a modified version of it, you must provide attribution to Red Hat Inc. and provide a link to the original.",
        "title": "Terms of Use"
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        "url": "https://bugzilla.redhat.com/show_bug.cgi?id=1667782"
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      {
        "category": "external",
        "summary": "1702717",
        "url": "https://bugzilla.redhat.com/show_bug.cgi?id=1702717"
      },
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        "category": "external",
        "summary": "1705312",
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        "summary": "Canonical URL",
        "url": "https://security.access.redhat.com/data/csaf/v2/advisories/2019/rhsa-2019_1206.json"
      }
    ],
    "title": "Red Hat Security Advisory: rhvm-setup-plugins security update",
    "tracking": {
      "current_release_date": "2026-05-29T21:24:20+00:00",
      "generator": {
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          "number": "1",
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          "number": "2",
          "summary": "Last updated version"
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        {
          "date": "2026-05-29T21:24:20+00:00",
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        "relates_to_product_reference": "7Server-RHV-S-4.2"
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      "cwe": {
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        "name": "Covert Storage Channel"
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      "discovery_date": "2018-11-06T00:00:00+00:00",
      "ids": [
        {
          "system_name": "Red Hat Bugzilla ID",
          "text": "1646781"
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      "notes": [
        {
          "category": "description",
          "text": "Modern Intel microprocessors implement hardware-level micro-optimizations to improve the performance of writing data back to CPU caches. The write operation is split into STA (STore Address) and STD (STore Data) sub-operations. These sub-operations allow the processor to hand-off address generation logic into these sub-operations for optimized writes. Both of these sub-operations write to a shared distributed processor structure called the \u0027processor store buffer\u0027. As a result, an unprivileged attacker could use this flaw to read private data resident within the CPU\u0027s processor store buffer.",
          "title": "Vulnerability description"
        },
        {
          "category": "summary",
          "text": "hardware: Microarchitectural Store Buffer Data Sampling (MSBDS)",
          "title": "Vulnerability summary"
        },
        {
          "category": "other",
          "text": "Red Hat Product Security is aware of this issue. Updates will be released as they become available. For additional information, please refer to the \u0027Vulnerability Response\u0027 URL.",
          "title": "Statement"
        },
        {
          "category": "general",
          "text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
          "title": "CVSS score applicability"
        }
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      "references": [
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          "category": "self",
          "summary": "Canonical URL",
          "url": "https://access.redhat.com/security/cve/CVE-2018-12126"
        },
        {
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          "summary": "RHBZ#1646781",
          "url": "https://bugzilla.redhat.com/show_bug.cgi?id=1646781"
        },
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          "summary": "RHSB-mds",
          "url": "https://access.redhat.com/security/vulnerabilities/mds"
        },
        {
          "category": "external",
          "summary": "https://www.cve.org/CVERecord?id=CVE-2018-12126",
          "url": "https://www.cve.org/CVERecord?id=CVE-2018-12126"
        },
        {
          "category": "external",
          "summary": "https://nvd.nist.gov/vuln/detail/CVE-2018-12126",
          "url": "https://nvd.nist.gov/vuln/detail/CVE-2018-12126"
        },
        {
          "category": "external",
          "summary": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00233.html",
          "url": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00233.html"
        }
      ],
      "release_date": "2019-05-14T17:00:00+00:00",
      "remediations": [
        {
          "category": "vendor_fix",
          "date": "2019-05-14T21:10:47+00:00",
          "details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/2974891",
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          ],
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          "url": "https://access.redhat.com/errata/RHSA-2019:1206"
        }
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      "scores": [
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            "attackComplexity": "LOW",
            "attackVector": "LOCAL",
            "availabilityImpact": "NONE",
            "baseScore": 6.5,
            "baseSeverity": "MEDIUM",
            "confidentialityImpact": "HIGH",
            "integrityImpact": "NONE",
            "privilegesRequired": "LOW",
            "scope": "CHANGED",
            "userInteraction": "NONE",
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            "version": "3.0"
          },
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          ]
        }
      ],
      "threats": [
        {
          "category": "impact",
          "details": "Moderate"
        }
      ],
      "title": "hardware: Microarchitectural Store Buffer Data Sampling (MSBDS)"
    },
    {
      "cve": "CVE-2018-12127",
      "cwe": {
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        "name": "Covert Timing Channel"
      },
      "discovery_date": "2019-01-21T00:00:00+00:00",
      "ids": [
        {
          "system_name": "Red Hat Bugzilla ID",
          "text": "1667782"
        }
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        {
          "category": "description",
          "text": "Microprocessors use a \u2018load port\u2019 subcomponent to perform load operations from memory or IO. During a load operation, the load port receives data from the memory or IO subsystem and then provides the data to the CPU registers and operations in the CPU\u2019s pipelines. Stale load operations results are stored in the \u0027load port\u0027 table until overwritten by newer operations. Certain load-port operations triggered by an attacker can be used to reveal data about previous stale requests leaking data back to the attacker via a timing side-channel.",
          "title": "Vulnerability description"
        },
        {
          "category": "summary",
          "text": "hardware: Micro-architectural Load Port Data Sampling - Information Leak (MLPDS)",
          "title": "Vulnerability summary"
        },
        {
          "category": "other",
          "text": "Red Hat Product Security is aware of this issue. Updates will be released as they become available. For additional information, please refer to the \u0027Vulnerability Response\u0027 URL.",
          "title": "Statement"
        },
        {
          "category": "general",
          "text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
          "title": "CVSS score applicability"
        }
      ],
      "product_status": {
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          "url": "https://access.redhat.com/security/cve/CVE-2018-12127"
        },
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          "summary": "RHBZ#1667782",
          "url": "https://bugzilla.redhat.com/show_bug.cgi?id=1667782"
        },
        {
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          "summary": "RHSB-mds",
          "url": "https://access.redhat.com/security/vulnerabilities/mds"
        },
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          "url": "https://www.cve.org/CVERecord?id=CVE-2018-12127"
        },
        {
          "category": "external",
          "summary": "https://nvd.nist.gov/vuln/detail/CVE-2018-12127",
          "url": "https://nvd.nist.gov/vuln/detail/CVE-2018-12127"
        },
        {
          "category": "external",
          "summary": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00233.html",
          "url": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00233.html"
        }
      ],
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      "remediations": [
        {
          "category": "vendor_fix",
          "date": "2019-05-14T21:10:47+00:00",
          "details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/2974891",
          "product_ids": [
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          ],
          "restart_required": {
            "category": "none"
          },
          "url": "https://access.redhat.com/errata/RHSA-2019:1206"
        }
      ],
      "scores": [
        {
          "cvss_v3": {
            "attackComplexity": "LOW",
            "attackVector": "LOCAL",
            "availabilityImpact": "NONE",
            "baseScore": 6.5,
            "baseSeverity": "MEDIUM",
            "confidentialityImpact": "HIGH",
            "integrityImpact": "NONE",
            "privilegesRequired": "LOW",
            "scope": "CHANGED",
            "userInteraction": "NONE",
            "vectorString": "CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:N/A:N",
            "version": "3.0"
          },
          "products": [
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          ]
        }
      ],
      "threats": [
        {
          "category": "impact",
          "details": "Moderate"
        }
      ],
      "title": "hardware: Micro-architectural Load Port Data Sampling - Information Leak (MLPDS)"
    },
    {
      "cve": "CVE-2018-12130",
      "cwe": {
        "id": "CWE-208",
        "name": "Observable Timing Discrepancy"
      },
      "discovery_date": "2018-11-06T00:00:00+00:00",
      "ids": [
        {
          "system_name": "Red Hat Bugzilla ID",
          "text": "1646784"
        }
      ],
      "notes": [
        {
          "category": "description",
          "text": "A flaw was found in the implementation of the \"fill buffer\", a mechanism used by modern CPUs when a cache-miss is made on L1 CPU cache. If an attacker can generate a load operation that would create a page fault, the execution will continue speculatively with incorrect data from the fill buffer while the data is fetched from higher level caches. This response time can be measured to infer data in the fill buffer.",
          "title": "Vulnerability description"
        },
        {
          "category": "summary",
          "text": "hardware: Microarchitectural Fill Buffer Data Sampling (MFBDS)",
          "title": "Vulnerability summary"
        },
        {
          "category": "other",
          "text": "Red Hat Product Security is aware of this issue. Updates will be released as they become available. For additional information, please refer to the \u0027Vulnerability Response\u0027 URL.",
          "title": "Statement"
        },
        {
          "category": "general",
          "text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
          "title": "CVSS score applicability"
        }
      ],
      "product_status": {
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      "references": [
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          "summary": "Canonical URL",
          "url": "https://access.redhat.com/security/cve/CVE-2018-12130"
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          "summary": "RHBZ#1646784",
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          "category": "external",
          "summary": "https://www.cve.org/CVERecord?id=CVE-2018-12130",
          "url": "https://www.cve.org/CVERecord?id=CVE-2018-12130"
        },
        {
          "category": "external",
          "summary": "https://nvd.nist.gov/vuln/detail/CVE-2018-12130",
          "url": "https://nvd.nist.gov/vuln/detail/CVE-2018-12130"
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      ],
      "release_date": "2019-05-14T17:00:00+00:00",
      "remediations": [
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          "category": "vendor_fix",
          "date": "2019-05-14T21:10:47+00:00",
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          ],
          "restart_required": {
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          },
          "url": "https://access.redhat.com/errata/RHSA-2019:1206"
        }
      ],
      "scores": [
        {
          "cvss_v3": {
            "attackComplexity": "LOW",
            "attackVector": "LOCAL",
            "availabilityImpact": "NONE",
            "baseScore": 6.2,
            "baseSeverity": "MEDIUM",
            "confidentialityImpact": "HIGH",
            "integrityImpact": "NONE",
            "privilegesRequired": "NONE",
            "scope": "UNCHANGED",
            "userInteraction": "NONE",
            "vectorString": "CVSS:3.0/AV:L/AC:L/PR:N/UI:N/S:U/C:H/I:N/A:N",
            "version": "3.0"
          },
          "products": [
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          ]
        }
      ],
      "threats": [
        {
          "category": "impact",
          "details": "Important"
        }
      ],
      "title": "hardware: Microarchitectural Fill Buffer Data Sampling (MFBDS)"
    },
    {
      "cve": "CVE-2019-11091",
      "cwe": {
        "id": "CWE-515",
        "name": "Covert Storage Channel"
      },
      "discovery_date": "2018-11-06T00:00:00+00:00",
      "ids": [
        {
          "system_name": "Red Hat Bugzilla ID",
          "text": "1705312"
        }
      ],
      "notes": [
        {
          "category": "description",
          "text": "Uncacheable memory on some microprocessors utilizing speculative execution may allow an authenticated user to potentially enable information disclosure via a side channel with local access.",
          "title": "Vulnerability description"
        },
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          "title": "Vulnerability description"
        },
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          "details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/2974891",
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          "text": "Modern Intel microprocessors implement hardware-level micro-optimizations to improve the performance of writing data back to CPU caches. The write operation is split into STA (STore Address) and STD (STore Data) sub-operations. These sub-operations allow the processor to hand-off address generation logic into these sub-operations for optimized writes. Both of these sub-operations write to a shared distributed processor structure called the \u0027processor store buffer\u0027. As a result, an unprivileged attacker could use this flaw to read private data resident within the CPU\u0027s processor store buffer.",
          "title": "Vulnerability description"
        },
        {
          "category": "summary",
          "text": "hardware: Microarchitectural Store Buffer Data Sampling (MSBDS)",
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        },
        {
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          "text": "Red Hat Product Security is aware of this issue. Updates will be released as they become available. For additional information, please refer to the \u0027Vulnerability Response\u0027 URL.",
          "title": "Statement"
        },
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          "text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
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          "text": "hardware: Micro-architectural Load Port Data Sampling - Information Leak (MLPDS)",
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          "title": "Statement"
        },
        {
          "category": "general",
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          "title": "Vulnerability description"
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          "text": "hardware: Microarchitectural Fill Buffer Data Sampling (MFBDS)",
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        },
        {
          "category": "other",
          "text": "Red Hat Product Security is aware of this issue. Updates will be released as they become available. For additional information, please refer to the \u0027Vulnerability Response\u0027 URL.",
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        {
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}