FKIE_CVE-2023-34326

Vulnerability from fkie_nvd - Published: 2024-01-05 17:15 - Updated: 2025-11-04 20:16
Severity ?
7.8 (High) - CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:H/I:H/A:H
7.8 (High) - CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:H/I:H/A:H
Summary
The caching invalidation guidelines from the AMD-Vi specification (48882—Rev 3.07-PUB—Oct 2022) is incorrect on some hardware, as devices will malfunction (see stale DMA mappings) if some fields of the DTE are updated but the IOMMU TLB is not flushed. Such stale DMA mappings can point to memory ranges not owned by the guest, thus allowing access to unindented memory regions.
References
security@xen.orghttps://xenbits.xenproject.org/xsa/advisory-442.htmlVendor Advisory
af854a3a-2127-422b-91ae-364da2661108http://xenbits.xen.org/xsa/advisory-442.html
af854a3a-2127-422b-91ae-364da2661108https://xenbits.xenproject.org/xsa/advisory-442.htmlVendor Advisory
Impacted products
Vendor Product Version
xen xen *
To clipboard 

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      "value": "The caching invalidation guidelines from the AMD-Vi specification (48882\u2014Rev\n3.07-PUB\u2014Oct 2022) is incorrect on some hardware, as devices will malfunction\n(see stale DMA mappings) if some fields of the DTE are updated but the IOMMU\nTLB is not flushed.\n\nSuch stale DMA mappings can point to memory ranges not owned by the guest, thus\nallowing access to unindented memory regions.\n"
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    }
  ],
  "id": "CVE-2023-34326",
  "lastModified": "2025-11-04T20:16:31.033",
  "metrics": {
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          "attackComplexity": "LOW",
          "attackVector": "LOCAL",
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          "confidentialityImpact": "HIGH",
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  "published": "2024-01-05T17:15:08.637",
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}


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