FKIE_CVE-2025-63384
Vulnerability from fkie_nvd - Published: 2025-11-10 20:15 - Updated: 2025-11-12 21:15
Severity ?
Summary
A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exception Return) instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode (M-mode) to Supervisor-mode (S-mode) as specified by the sstatus.SPP bit, the processor incorrectly remains in M-mode, leading to a critical privilege retention vulnerability.
References
Impacted products
| Vendor | Product | Version |
|---|
{
"cveTags": [],
"descriptions": [
{
"lang": "en",
"value": "A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exception Return) instruction fails to correctly transition the processor\u0027s privilege level. Instead of downgrading from Machine-mode (M-mode) to Supervisor-mode (S-mode) as specified by the sstatus.SPP bit, the processor incorrectly remains in M-mode, leading to a critical privilege retention vulnerability."
},
{
"lang": "es",
"value": "Se descubri\u00f3 una vulnerabilidad en RISC-V Rocket-Chip v1.6 y versiones anteriores, donde la instrucci\u00f3n SRET (Supervisor-mode Exception Return) no logra transicionar correctamente el nivel de privilegio del procesador. En lugar de bajar de categor\u00eda desde el modo M\u00e1quina (M-mode) a modo Supervisor (S-mode) seg\u00fan lo especificado por el bit sstatus.SPP, el procesador permanece incorrectamente en M-mode, lo que lleva a una vulnerabilidad cr\u00edtica de retenci\u00f3n de privilegios."
}
],
"id": "CVE-2025-63384",
"lastModified": "2025-11-12T21:15:52.220",
"metrics": {
"cvssMetricV31": [
{
"cvssData": {
"attackComplexity": "LOW",
"attackVector": "NETWORK",
"availabilityImpact": "NONE",
"baseScore": 6.5,
"baseSeverity": "MEDIUM",
"confidentialityImpact": "HIGH",
"integrityImpact": "NONE",
"privilegesRequired": "LOW",
"scope": "UNCHANGED",
"userInteraction": "NONE",
"vectorString": "CVSS:3.1/AV:N/AC:L/PR:L/UI:N/S:U/C:H/I:N/A:N",
"version": "3.1"
},
"exploitabilityScore": 2.8,
"impactScore": 3.6,
"source": "134c704f-9b21-4f2e-91b3-4a467353bcc0",
"type": "Secondary"
}
]
},
"published": "2025-11-10T20:15:49.013",
"references": [
{
"source": "cve@mitre.org",
"url": "https://github.com/107040503/RISC-V-Vulnerability-Disclosure_SRET"
},
{
"source": "cve@mitre.org",
"url": "https://github.com/chipsalliance/rocket-chip.git"
}
],
"sourceIdentifier": "cve@mitre.org",
"vulnStatus": "Awaiting Analysis",
"weaknesses": [
{
"description": [
{
"lang": "en",
"value": "CWE-266"
}
],
"source": "134c704f-9b21-4f2e-91b3-4a467353bcc0",
"type": "Secondary"
}
]
}
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Sightings
| Author | Source | Type | Date |
|---|
Nomenclature
- Seen: The vulnerability was mentioned, discussed, or observed by the user.
- Confirmed: The vulnerability has been validated from an analyst's perspective.
- Published Proof of Concept: A public proof of concept is available for this vulnerability.
- Exploited: The vulnerability was observed as exploited by the user who reported the sighting.
- Patched: The vulnerability was observed as successfully patched by the user who reported the sighting.
- Not exploited: The vulnerability was not observed as exploited by the user who reported the sighting.
- Not confirmed: The user expressed doubt about the validity of the vulnerability.
- Not patched: The vulnerability was not observed as successfully patched by the user who reported the sighting.
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