Common Weakness Enumeration

CWE-1342

Allowed

Information Exposure through Microarchitectural State after Transient Execution

Abstraction: Base · Status: Incomplete

API response cwe.mitre.org

The processor does not properly clear microarchitectural state after incorrect microcode assists or speculative execution, resulting in transient execution.

3 vulnerabilities reference this CWE, most recent first.

CVE-2023-28746 (GCVE-0-2023-28746)

Vulnerability from cvelistv5 – Published: 2024-03-14 16:45 – Updated: 2026-05-12 10:52
VLAI
Summary
Information exposure through microarchitectural state after transient execution from some register files for some Intel(R) Atom(R) Processors may allow an authenticated user to potentially enable information disclosure via local access.
Severity
6.5 (Medium)
CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:N/A:N
SSVC
Exploitation: none Automatable: no Technical Impact: partial
CISA Coordinator (v2.0.3)
CWE
  • information disclosure
  • CWE-1342 - Information exposure through microarchitectural state after transient execution from some register files
Assigner
References
Impacted products
Show details on NVD website
To clipboard 

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CVE-2022-40982 (GCVE-0-2022-40982)

Vulnerability from cvelistv5 – Published: 2023-08-11 02:37 – Updated: 2025-02-13 16:33
VLAI
Summary
Information exposure through microarchitectural state after transient execution in certain vector execution units for some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure via local access.
Severity
6.5 (Medium)
CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:N/A:N
SSVC
Exploitation: none Automatable: no Technical Impact: partial
CISA Coordinator (v2.0.3)
CWE
  • information disclosure
  • CWE-1342 - Information exposure through microarchitectural state after transient execution
Assigner
References
Impacted products
Vendor Product Version
n/a Intel(R) Processors Affected: See references
Show details on NVD website
To clipboard 

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GHSA-36C8-X5G7-W9X4

Vulnerability from github – Published: 2024-03-14 18:30 – Updated: 2026-05-12 12:31
VLAI
Details

Information exposure through microarchitectural state after transient execution from some register files for some Intel(R) Atom(R) Processors may allow an authenticated user to potentially enable information disclosure via local access.

Severity
6.5 (Medium)
CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:N/A:N
Show details on source website
To clipboard 

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Mitigation
Architecture and Design Requirements

Hardware ensures that no illegal data flows from faulting micro-ops exists at the microarchitectural level.

Mitigation
Build and Compilation

Include instructions that explicitly remove traces of unneeded computations from software interactions with microarchitectural elements e.g. lfence, sfence, mfence, clflush.

CAPEC-696: Load Value Injection

An adversary exploits a hardware design flaw in a CPU implementation of transient instruction execution in which a faulting or assisted load instruction transiently forwards adversary-controlled data from microarchitectural buffers. By inducing a page fault or microcode assist during victim execution, an adversary can force legitimate victim execution to operate on the adversary-controlled data which is stored in the microarchitectural buffers. The adversary can then use existing code gadgets and side channel analysis to discover victim secrets that have not yet been flushed from microarchitectural state or hijack the system control flow.

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