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CVE-2018-12207 (GCVE-0-2018-12207)
Vulnerability from cvelistv5 – Published: 2019-11-14 19:08 – Updated: 2024-08-05 08:30- Denial of Service
| Vendor | Product | Version | |
|---|---|---|---|
| n/a | 2019.2 IPU – Intel(R) Processor Machine Check Error |
Affected:
See provided reference
|
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"descriptions": "[{\"lang\": \"en\", \"value\": \"Improper invalidation for page table updates by a virtual guest operating system for multiple Intel(R) Processors may allow an authenticated user to potentially enable denial of service of the host system via local access.\"}, {\"lang\": \"es\", \"value\": \"Una invalidaci\\u00f3n inapropiada de las actualizaciones de la tabla de p\\u00e1ginas por parte de un sistema operativo invitado virtual para m\\u00faltiples procesadores Intel\\u00ae puede habilitar a un usuario autenticado para permitir potencialmente una denegaci\\u00f3n de servicio del sistema host por medio de un acceso local.\"}]",
"id": "CVE-2018-12207",
"lastModified": "2024-11-21T03:44:45.313",
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"published": "2019-11-14T20:15:11.133",
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"sourceIdentifier": "secure@intel.com",
"vulnStatus": "Modified",
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}
}
RHSA-2019_3838
Vulnerability from csaf_redhat - Published: 2019-11-12 20:51 - Updated: 2024-11-15 03:17A flaw was found in the way Intel CPUs handle inconsistency between, virtual to physical memory address translations in CPU's local cache and system software's Paging structure entries. A privileged guest user may use this flaw to induce a hardware Machine Check Error on the host processor, resulting in a severe DoS scenario by halting the processor. System software like OS OR Virtual Machine Monitor (VMM) use virtual memory system for storing program instructions and data in memory. Virtual Memory system uses Paging structures like Page Tables and Page Directories to manage system memory. The processor's Memory Management Unit (MMU) uses Paging structure entries to translate program's virtual memory addresses to physical memory addresses. The processor stores these address translations into its local cache buffer called - Translation Lookaside Buffer (TLB). TLB has two parts, one for instructions and other for data addresses. System software can modify its Paging structure entries to change address mappings OR certain attributes like page size etc. Upon such Paging structure alterations in memory, system software must invalidate the corresponding address translations in the processor's TLB cache. But before this TLB invalidation takes place, a privileged guest user may trigger an instruction fetch operation, which could use an already cached, but now invalid, virtual to physical address translation from Instruction TLB (ITLB). Thus accessing an invalid physical memory address and resulting in halting the processor due to the Machine Check Error (MCE) on Page Size Change.
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| Unresolved product id: 7Server-optional-7.5.EUS:kernel-debuginfo-common-ppc64-0:3.10.0-862.43.2.el7.ppc64 | — |
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A flaw was found in Intel graphics hardware (GPU) where a local attacker with the ability to issue an ioctl could trigger a hardware level crash if MMIO registers were read while the graphics card was in a low-power state. This creates a denial of service situation and the GPU and connected displays will remain unusable until a reboot occurs.
| Product | Identifier | Version | Remediation |
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| Unresolved product id: 7ComputeNode-7.5.EUS:kernel-0:3.10.0-862.43.2.el7.ppc64 | — |
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| Unresolved product id: 7ComputeNode-7.5.EUS:kernel-0:3.10.0-862.43.2.el7.src | — |
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| Unresolved product id: 7ComputeNode-7.5.EUS:kernel-debug-debuginfo-0:3.10.0-862.43.2.el7.ppc64 | — |
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| Unresolved product id: 7ComputeNode-7.5.EUS:kernel-debug-devel-0:3.10.0-862.43.2.el7.x86_64 | — |
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| Unresolved product id: 7ComputeNode-7.5.EUS:kernel-debuginfo-0:3.10.0-862.43.2.el7.ppc64 | — |
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| Unresolved product id: 7ComputeNode-7.5.EUS:kernel-debuginfo-common-ppc64-0:3.10.0-862.43.2.el7.ppc64 | — |
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| Unresolved product id: 7ComputeNode-7.5.EUS:kernel-debuginfo-common-ppc64le-0:3.10.0-862.43.2.el7.ppc64le | — |
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| Unresolved product id: 7ComputeNode-7.5.EUS:kernel-debuginfo-common-s390x-0:3.10.0-862.43.2.el7.s390x | — |
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| Unresolved product id: 7ComputeNode-7.5.EUS:kernel-debuginfo-common-x86_64-0:3.10.0-862.43.2.el7.x86_64 | — |
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| Unresolved product id: 7ComputeNode-7.5.EUS:kernel-devel-0:3.10.0-862.43.2.el7.x86_64 | — |
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| Unresolved product id: 7ComputeNode-7.5.EUS:kernel-doc-0:3.10.0-862.43.2.el7.noarch | — |
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| Unresolved product id: 7ComputeNode-7.5.EUS:kernel-headers-0:3.10.0-862.43.2.el7.s390x | — |
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| Unresolved product id: 7ComputeNode-7.5.EUS:kernel-headers-0:3.10.0-862.43.2.el7.x86_64 | — |
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| Unresolved product id: 7ComputeNode-7.5.EUS:kernel-kdump-0:3.10.0-862.43.2.el7.s390x | — |
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| Unresolved product id: 7ComputeNode-7.5.EUS:kernel-kdump-debuginfo-0:3.10.0-862.43.2.el7.s390x | — |
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| Unresolved product id: 7ComputeNode-7.5.EUS:kernel-kdump-devel-0:3.10.0-862.43.2.el7.s390x | — |
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| Unresolved product id: 7ComputeNode-7.5.EUS:kernel-tools-0:3.10.0-862.43.2.el7.ppc64 | — |
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| Unresolved product id: 7ComputeNode-7.5.EUS:kernel-tools-0:3.10.0-862.43.2.el7.ppc64le | — |
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| Unresolved product id: 7ComputeNode-7.5.EUS:kernel-tools-0:3.10.0-862.43.2.el7.x86_64 | — |
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| Unresolved product id: 7ComputeNode-7.5.EUS:kernel-tools-debuginfo-0:3.10.0-862.43.2.el7.ppc64 | — |
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| Unresolved product id: 7ComputeNode-7.5.EUS:kernel-tools-debuginfo-0:3.10.0-862.43.2.el7.ppc64le | — |
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| Unresolved product id: 7ComputeNode-7.5.EUS:kernel-tools-debuginfo-0:3.10.0-862.43.2.el7.x86_64 | — |
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| Unresolved product id: 7ComputeNode-7.5.EUS:kernel-tools-libs-0:3.10.0-862.43.2.el7.ppc64 | — |
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| Unresolved product id: 7ComputeNode-7.5.EUS:kernel-tools-libs-0:3.10.0-862.43.2.el7.ppc64le | — |
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| Unresolved product id: 7ComputeNode-7.5.EUS:kernel-tools-libs-0:3.10.0-862.43.2.el7.x86_64 | — |
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| Unresolved product id: 7ComputeNode-7.5.EUS:kernel-tools-libs-devel-0:3.10.0-862.43.2.el7.ppc64 | — |
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| Unresolved product id: 7ComputeNode-7.5.EUS:perf-0:3.10.0-862.43.2.el7.ppc64 | — |
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| Unresolved product id: 7ComputeNode-7.5.EUS:perf-debuginfo-0:3.10.0-862.43.2.el7.ppc64 | — |
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| Unresolved product id: 7ComputeNode-7.5.EUS:perf-debuginfo-0:3.10.0-862.43.2.el7.ppc64le | — |
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| Unresolved product id: 7ComputeNode-7.5.EUS:perf-debuginfo-0:3.10.0-862.43.2.el7.s390x | — |
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| Unresolved product id: 7ComputeNode-7.5.EUS:perf-debuginfo-0:3.10.0-862.43.2.el7.x86_64 | — |
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| Unresolved product id: 7ComputeNode-7.5.EUS:python-perf-0:3.10.0-862.43.2.el7.ppc64 | — |
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| Unresolved product id: 7ComputeNode-7.5.EUS:python-perf-0:3.10.0-862.43.2.el7.ppc64le | — |
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| Unresolved product id: 7ComputeNode-7.5.EUS:python-perf-0:3.10.0-862.43.2.el7.s390x | — |
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| Unresolved product id: 7ComputeNode-7.5.EUS:python-perf-0:3.10.0-862.43.2.el7.x86_64 | — |
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| Unresolved product id: 7ComputeNode-7.5.EUS:python-perf-debuginfo-0:3.10.0-862.43.2.el7.ppc64 | — |
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A flaw was found in the way Intel CPUs handle speculative execution of instructions when the TSX Asynchronous Abort (TAA) error occurs. A local authenticated attacker with the ability to monitor execution times could infer the TSX memory state by comparing abort execution times. This could allow information disclosure via this observed side-channel for any TSX transaction being executed while an attacker is able to observe abort timing. Intel's Transactional Synchronisation Extensions (TSX) are set of instructions which enable transactional memory support to improve performance of the multi-threaded applications, in the lock-protected critical sections. The CPU executes instructions in the critical-sections as transactions, while ensuring their atomic state. When such transaction execution is unsuccessful, the processor cannot ensure atomic updates to the transaction memory, so the processor rolls back or aborts such transaction execution. While TSX Asynchronous Abort (TAA) is pending, CPU may continue to read data from architectural buffers and pass it to the dependent speculative operations. This may cause information leakage via speculative side-channel means, which is quite similar to the Microarchitectural Data Sampling (MDS) issue.
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| Unresolved product id: 7ComputeNode-7.5.EUS:kernel-doc-0:3.10.0-862.43.2.el7.noarch | — |
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{
"document": {
"aggregate_severity": {
"namespace": "https://access.redhat.com/security/updates/classification/",
"text": "Important"
},
"category": "csaf_security_advisory",
"csaf_version": "2.0",
"distribution": {
"text": "Copyright \u00a9 Red Hat, Inc. All rights reserved.",
"tlp": {
"label": "WHITE",
"url": "https://www.first.org/tlp/"
}
},
"lang": "en",
"notes": [
{
"category": "summary",
"text": "An update for kernel is now available for Red Hat Enterprise Linux 7.5 Extended Update Support.\n\nRed Hat Product Security has rated this update as having a security impact of Important. A Common Vulnerability Scoring System (CVSS) base score, which gives a detailed severity rating, is available for each vulnerability from the CVE link(s) in the References section.",
"title": "Topic"
},
{
"category": "general",
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"vulnerabilities": [
{
"acknowledgments": [
{
"names": [
"Intel"
]
},
{
"names": [
"Deepak Gupta"
],
"summary": "Acknowledged by upstream."
}
],
"cve": "CVE-2018-12207",
"cwe": {
"id": "CWE-226",
"name": "Sensitive Information in Resource Not Removed Before Reuse"
},
"discovery_date": "2018-11-06T00:00:00+00:00",
"ids": [
{
"system_name": "Red Hat Bugzilla ID",
"text": "1646768"
}
],
"notes": [
{
"category": "description",
"text": "A flaw was found in the way Intel CPUs handle inconsistency between, virtual to physical memory address translations in CPU\u0027s local cache and system software\u0027s Paging structure entries. A privileged guest user may use this flaw to induce a hardware Machine Check Error on the host processor, resulting in a severe DoS scenario by halting the processor.\r\n\r\nSystem software like OS OR Virtual Machine Monitor (VMM) use virtual memory system for storing program instructions and data in memory. Virtual Memory system uses Paging structures like Page Tables and Page Directories to manage system memory. The processor\u0027s Memory Management Unit (MMU) uses Paging structure entries to translate program\u0027s virtual memory addresses to physical memory addresses. The processor stores these address translations into its local cache buffer called - Translation Lookaside Buffer (TLB). TLB has two parts, one for instructions and other for data addresses.\r\n\r\nSystem software can modify its Paging structure entries to change address mappings OR certain attributes like page size etc. Upon such Paging structure alterations in memory, system software must invalidate the corresponding address translations in the processor\u0027s TLB cache. But before this TLB invalidation takes place, a privileged guest user may trigger an instruction fetch operation, which could use an already cached, but now invalid, virtual to physical address translation from Instruction TLB (ITLB). Thus accessing an invalid physical memory address and resulting in halting the processor due to the Machine Check Error (MCE) on Page Size Change.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "hw: Machine Check Error on Page Size Change (IFU)",
"title": "Vulnerability summary"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
],
"product_status": {
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]
},
"references": [
{
"category": "self",
"summary": "Canonical URL",
"url": "https://access.redhat.com/security/cve/CVE-2018-12207"
},
{
"category": "external",
"summary": "RHBZ#1646768",
"url": "https://bugzilla.redhat.com/show_bug.cgi?id=1646768"
},
{
"category": "external",
"summary": "RHSB-ifu-page-mce",
"url": "https://access.redhat.com/security/vulnerabilities/ifu-page-mce"
},
{
"category": "external",
"summary": "https://www.cve.org/CVERecord?id=CVE-2018-12207",
"url": "https://www.cve.org/CVERecord?id=CVE-2018-12207"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2018-12207",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2018-12207"
},
{
"category": "external",
"summary": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00210.html",
"url": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00210.html"
}
],
"release_date": "2019-11-12T18:00:00+00:00",
"remediations": [
{
"category": "vendor_fix",
"date": "2019-11-12T20:51:27+00:00",
"details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/11258\n\nThe system must be rebooted for this update to take effect.",
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],
"restart_required": {
"category": "machine"
},
"url": "https://access.redhat.com/errata/RHSA-2019:3838"
},
{
"category": "workaround",
"details": "For mitigation related information, please refer to the Red Hat vulnerability article: https://access.redhat.com/security/vulnerabilities/ifu-page-mce .",
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}
],
"scores": [
{
"cvss_v3": {
"attackComplexity": "LOW",
"attackVector": "LOCAL",
"availabilityImpact": "HIGH",
"baseScore": 6.5,
"baseSeverity": "MEDIUM",
"confidentialityImpact": "NONE",
"integrityImpact": "NONE",
"privilegesRequired": "LOW",
"scope": "CHANGED",
"userInteraction": "NONE",
"vectorString": "CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:N/I:N/A:H",
"version": "3.0"
},
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}
],
"threats": [
{
"category": "impact",
"details": "Important"
}
],
"title": "hw: Machine Check Error on Page Size Change (IFU)"
},
{
"acknowledgments": [
{
"names": [
"Intel"
]
}
],
"cve": "CVE-2019-0154",
"cwe": {
"id": "CWE-284",
"name": "Improper Access Control"
},
"discovery_date": "2019-06-27T00:00:00+00:00",
"ids": [
{
"system_name": "Red Hat Bugzilla ID",
"text": "1724393"
}
],
"notes": [
{
"category": "description",
"text": "A flaw was found in Intel graphics hardware (GPU) where a local attacker with the ability to issue an ioctl could trigger a hardware level crash if MMIO registers were read while the graphics card was in a low-power state. This creates a denial of service situation and the GPU and connected displays will remain unusable until a reboot occurs.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "hw: Intel GPU Denial Of Service while accessing MMIO in lower power state",
"title": "Vulnerability summary"
},
{
"category": "other",
"text": "Intel plans to release BIOS firmware to correct this issue. Red Hat\u0027s kernel update should mitigate this vulnerability. Some older hardware will not have BIOS firmware update and will rely on operating system level protection to prevent access while the device is in low-power states. For more information see https://access.redhat.com/solutions/i915-graphics",
"title": "Statement"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
],
"product_status": {
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},
"references": [
{
"category": "self",
"summary": "Canonical URL",
"url": "https://access.redhat.com/security/cve/CVE-2019-0154"
},
{
"category": "external",
"summary": "RHBZ#1724393",
"url": "https://bugzilla.redhat.com/show_bug.cgi?id=1724393"
},
{
"category": "external",
"summary": "https://www.cve.org/CVERecord?id=CVE-2019-0154",
"url": "https://www.cve.org/CVERecord?id=CVE-2019-0154"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2019-0154",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2019-0154"
},
{
"category": "external",
"summary": "https://access.redhat.com/solutions/i915-graphics",
"url": "https://access.redhat.com/solutions/i915-graphics"
},
{
"category": "external",
"summary": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00260.html",
"url": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00260.html"
}
],
"release_date": "2019-11-12T18:00:00+00:00",
"remediations": [
{
"category": "vendor_fix",
"date": "2019-11-12T20:51:27+00:00",
"details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/11258\n\nThe system must be rebooted for this update to take effect.",
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],
"restart_required": {
"category": "machine"
},
"url": "https://access.redhat.com/errata/RHSA-2019:3838"
},
{
"category": "workaround",
"details": "Preventing loading of the i915 kernel module will prevent attackers from using this exploit against the system however the power management functionality of the card will be disabled and the system may draw additional power. See this KCS article (https://access.redhat.com/solutions/41278) for instructions on how to disable a kernel module. Graphical displays may also be at low resolution or not work correctly. This mitigation may not be suitable if running graphical tools locally is required.",
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}
],
"scores": [
{
"cvss_v3": {
"attackComplexity": "LOW",
"attackVector": "LOCAL",
"availabilityImpact": "HIGH",
"baseScore": 6.5,
"baseSeverity": "MEDIUM",
"confidentialityImpact": "NONE",
"integrityImpact": "NONE",
"privilegesRequired": "LOW",
"scope": "CHANGED",
"userInteraction": "NONE",
"vectorString": "CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:N/I:N/A:H",
"version": "3.0"
},
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}
],
"threats": [
{
"category": "impact",
"details": "Moderate"
}
],
"title": "hw: Intel GPU Denial Of Service while accessing MMIO in lower power state"
},
{
"acknowledgments": [
{
"names": [
"Intel"
]
}
],
"cve": "CVE-2019-11135",
"cwe": {
"id": "CWE-203",
"name": "Observable Discrepancy"
},
"discovery_date": "2019-09-18T00:00:00+00:00",
"ids": [
{
"system_name": "Red Hat Bugzilla ID",
"text": "1753062"
}
],
"notes": [
{
"category": "description",
"text": "A flaw was found in the way Intel CPUs handle speculative execution of instructions when the TSX Asynchronous Abort (TAA) error occurs. A local authenticated attacker with the ability to monitor execution times could infer the TSX memory state by comparing abort execution times. This could allow information disclosure via this observed side-channel for any TSX transaction being executed while an attacker is able to observe abort timing.\r\n\r\nIntel\u0027s Transactional Synchronisation Extensions (TSX) are set of instructions which enable transactional memory support to improve performance of the multi-threaded applications, in the lock-protected critical sections. The CPU executes instructions in the critical-sections as transactions, while ensuring their atomic state. When such transaction execution is unsuccessful, the processor cannot ensure atomic updates to the transaction memory, so the processor rolls back or aborts such transaction execution.\r\n\r\nWhile TSX Asynchronous Abort (TAA) is pending, CPU may continue to read data from architectural buffers and pass it to the dependent speculative operations. This may cause information leakage via speculative side-channel means, which is quite similar to the Microarchitectural Data Sampling (MDS) issue.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "hw: TSX Transaction Asynchronous Abort (TAA)",
"title": "Vulnerability summary"
},
{
"category": "other",
"text": "libvirt and qemu-kvm on Red Hat Enterprise Linux 6 are not affected by this vulnerability as they do not support MSR-based CPU features.",
"title": "Statement"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
],
"product_status": {
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]
},
"references": [
{
"category": "self",
"summary": "Canonical URL",
"url": "https://access.redhat.com/security/cve/CVE-2019-11135"
},
{
"category": "external",
"summary": "RHBZ#1753062",
"url": "https://bugzilla.redhat.com/show_bug.cgi?id=1753062"
},
{
"category": "external",
"summary": "https://www.cve.org/CVERecord?id=CVE-2019-11135",
"url": "https://www.cve.org/CVERecord?id=CVE-2019-11135"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2019-11135",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2019-11135"
},
{
"category": "external",
"summary": "https://access.redhat.com/solutions/tsx-asynchronousabort",
"url": "https://access.redhat.com/solutions/tsx-asynchronousabort"
},
{
"category": "external",
"summary": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00270.html",
"url": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00270.html"
}
],
"release_date": "2019-11-12T18:00:00+00:00",
"remediations": [
{
"category": "vendor_fix",
"date": "2019-11-12T20:51:27+00:00",
"details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/11258\n\nThe system must be rebooted for this update to take effect.",
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],
"restart_required": {
"category": "machine"
},
"url": "https://access.redhat.com/errata/RHSA-2019:3838"
},
{
"category": "workaround",
"details": "For mitigation related information, please refer to the Red Hat Knowledgebase article: https://access.redhat.com/solutions/tsx-asynchronousabort",
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}
],
"scores": [
{
"cvss_v3": {
"attackComplexity": "LOW",
"attackVector": "LOCAL",
"availabilityImpact": "NONE",
"baseScore": 6.5,
"baseSeverity": "MEDIUM",
"confidentialityImpact": "HIGH",
"integrityImpact": "NONE",
"privilegesRequired": "LOW",
"scope": "CHANGED",
"userInteraction": "NONE",
"vectorString": "CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:N/A:N",
"version": "3.0"
},
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]
}
],
"threats": [
{
"category": "impact",
"details": "Moderate"
}
],
"title": "hw: TSX Transaction Asynchronous Abort (TAA)"
}
]
}
RHSA-2019_3839
Vulnerability from csaf_redhat - Published: 2019-11-12 21:37 - Updated: 2024-11-15 03:17A flaw was found in the way Intel CPUs handle inconsistency between, virtual to physical memory address translations in CPU's local cache and system software's Paging structure entries. A privileged guest user may use this flaw to induce a hardware Machine Check Error on the host processor, resulting in a severe DoS scenario by halting the processor. System software like OS OR Virtual Machine Monitor (VMM) use virtual memory system for storing program instructions and data in memory. Virtual Memory system uses Paging structures like Page Tables and Page Directories to manage system memory. The processor's Memory Management Unit (MMU) uses Paging structure entries to translate program's virtual memory addresses to physical memory addresses. The processor stores these address translations into its local cache buffer called - Translation Lookaside Buffer (TLB). TLB has two parts, one for instructions and other for data addresses. System software can modify its Paging structure entries to change address mappings OR certain attributes like page size etc. Upon such Paging structure alterations in memory, system software must invalidate the corresponding address translations in the processor's TLB cache. But before this TLB invalidation takes place, a privileged guest user may trigger an instruction fetch operation, which could use an already cached, but now invalid, virtual to physical address translation from Instruction TLB (ITLB). Thus accessing an invalid physical memory address and resulting in halting the processor due to the Machine Check Error (MCE) on Page Size Change.
| Product | Identifier | Version | Remediation |
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| Unresolved product id: 7Server-7.4.AUS:kernel-0:3.10.0-693.60.2.el7.src | — |
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| Unresolved product id: 7Server-7.4.AUS:kernel-tools-0:3.10.0-693.60.2.el7.x86_64 | — |
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| Unresolved product id: 7Server-7.4.AUS:kernel-tools-debuginfo-0:3.10.0-693.60.2.el7.x86_64 | — |
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| Unresolved product id: 7Server-7.4.AUS:perf-debuginfo-0:3.10.0-693.60.2.el7.x86_64 | — |
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| Unresolved product id: 7Server-7.4.E4S:kernel-0:3.10.0-693.60.2.el7.ppc64le | — |
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| Unresolved product id: 7Server-7.4.E4S:kernel-0:3.10.0-693.60.2.el7.src | — |
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A flaw was found in Intel graphics hardware (GPU) where a local attacker with the ability to issue an ioctl could trigger a hardware level crash if MMIO registers were read while the graphics card was in a low-power state. This creates a denial of service situation and the GPU and connected displays will remain unusable until a reboot occurs.
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A flaw was found in the way Intel CPUs handle speculative execution of instructions when the TSX Asynchronous Abort (TAA) error occurs. A local authenticated attacker with the ability to monitor execution times could infer the TSX memory state by comparing abort execution times. This could allow information disclosure via this observed side-channel for any TSX transaction being executed while an attacker is able to observe abort timing. Intel's Transactional Synchronisation Extensions (TSX) are set of instructions which enable transactional memory support to improve performance of the multi-threaded applications, in the lock-protected critical sections. The CPU executes instructions in the critical-sections as transactions, while ensuring their atomic state. When such transaction execution is unsuccessful, the processor cannot ensure atomic updates to the transaction memory, so the processor rolls back or aborts such transaction execution. While TSX Asynchronous Abort (TAA) is pending, CPU may continue to read data from architectural buffers and pass it to the dependent speculative operations. This may cause information leakage via speculative side-channel means, which is quite similar to the Microarchitectural Data Sampling (MDS) issue.
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{
"acknowledgments": [
{
"names": [
"Intel"
]
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{
"names": [
"Deepak Gupta"
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"summary": "Acknowledged by upstream."
}
],
"cve": "CVE-2018-12207",
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"id": "CWE-226",
"name": "Sensitive Information in Resource Not Removed Before Reuse"
},
"discovery_date": "2018-11-06T00:00:00+00:00",
"ids": [
{
"system_name": "Red Hat Bugzilla ID",
"text": "1646768"
}
],
"notes": [
{
"category": "description",
"text": "A flaw was found in the way Intel CPUs handle inconsistency between, virtual to physical memory address translations in CPU\u0027s local cache and system software\u0027s Paging structure entries. A privileged guest user may use this flaw to induce a hardware Machine Check Error on the host processor, resulting in a severe DoS scenario by halting the processor.\r\n\r\nSystem software like OS OR Virtual Machine Monitor (VMM) use virtual memory system for storing program instructions and data in memory. Virtual Memory system uses Paging structures like Page Tables and Page Directories to manage system memory. The processor\u0027s Memory Management Unit (MMU) uses Paging structure entries to translate program\u0027s virtual memory addresses to physical memory addresses. The processor stores these address translations into its local cache buffer called - Translation Lookaside Buffer (TLB). TLB has two parts, one for instructions and other for data addresses.\r\n\r\nSystem software can modify its Paging structure entries to change address mappings OR certain attributes like page size etc. Upon such Paging structure alterations in memory, system software must invalidate the corresponding address translations in the processor\u0027s TLB cache. But before this TLB invalidation takes place, a privileged guest user may trigger an instruction fetch operation, which could use an already cached, but now invalid, virtual to physical address translation from Instruction TLB (ITLB). Thus accessing an invalid physical memory address and resulting in halting the processor due to the Machine Check Error (MCE) on Page Size Change.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "hw: Machine Check Error on Page Size Change (IFU)",
"title": "Vulnerability summary"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
],
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},
"references": [
{
"category": "self",
"summary": "Canonical URL",
"url": "https://access.redhat.com/security/cve/CVE-2018-12207"
},
{
"category": "external",
"summary": "RHBZ#1646768",
"url": "https://bugzilla.redhat.com/show_bug.cgi?id=1646768"
},
{
"category": "external",
"summary": "RHSB-ifu-page-mce",
"url": "https://access.redhat.com/security/vulnerabilities/ifu-page-mce"
},
{
"category": "external",
"summary": "https://www.cve.org/CVERecord?id=CVE-2018-12207",
"url": "https://www.cve.org/CVERecord?id=CVE-2018-12207"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2018-12207",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2018-12207"
},
{
"category": "external",
"summary": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00210.html",
"url": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00210.html"
}
],
"release_date": "2019-11-12T18:00:00+00:00",
"remediations": [
{
"category": "vendor_fix",
"date": "2019-11-12T21:37:14+00:00",
"details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/11258\n\nThe system must be rebooted for this update to take effect.",
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],
"restart_required": {
"category": "machine"
},
"url": "https://access.redhat.com/errata/RHSA-2019:3839"
},
{
"category": "workaround",
"details": "For mitigation related information, please refer to the Red Hat vulnerability article: https://access.redhat.com/security/vulnerabilities/ifu-page-mce .",
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}
],
"scores": [
{
"cvss_v3": {
"attackComplexity": "LOW",
"attackVector": "LOCAL",
"availabilityImpact": "HIGH",
"baseScore": 6.5,
"baseSeverity": "MEDIUM",
"confidentialityImpact": "NONE",
"integrityImpact": "NONE",
"privilegesRequired": "LOW",
"scope": "CHANGED",
"userInteraction": "NONE",
"vectorString": "CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:N/I:N/A:H",
"version": "3.0"
},
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],
"threats": [
{
"category": "impact",
"details": "Important"
}
],
"title": "hw: Machine Check Error on Page Size Change (IFU)"
},
{
"acknowledgments": [
{
"names": [
"Intel"
]
}
],
"cve": "CVE-2019-0154",
"cwe": {
"id": "CWE-284",
"name": "Improper Access Control"
},
"discovery_date": "2019-06-27T00:00:00+00:00",
"ids": [
{
"system_name": "Red Hat Bugzilla ID",
"text": "1724393"
}
],
"notes": [
{
"category": "description",
"text": "A flaw was found in Intel graphics hardware (GPU) where a local attacker with the ability to issue an ioctl could trigger a hardware level crash if MMIO registers were read while the graphics card was in a low-power state. This creates a denial of service situation and the GPU and connected displays will remain unusable until a reboot occurs.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "hw: Intel GPU Denial Of Service while accessing MMIO in lower power state",
"title": "Vulnerability summary"
},
{
"category": "other",
"text": "Intel plans to release BIOS firmware to correct this issue. Red Hat\u0027s kernel update should mitigate this vulnerability. Some older hardware will not have BIOS firmware update and will rely on operating system level protection to prevent access while the device is in low-power states. For more information see https://access.redhat.com/solutions/i915-graphics",
"title": "Statement"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
],
"product_status": {
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},
"references": [
{
"category": "self",
"summary": "Canonical URL",
"url": "https://access.redhat.com/security/cve/CVE-2019-0154"
},
{
"category": "external",
"summary": "RHBZ#1724393",
"url": "https://bugzilla.redhat.com/show_bug.cgi?id=1724393"
},
{
"category": "external",
"summary": "https://www.cve.org/CVERecord?id=CVE-2019-0154",
"url": "https://www.cve.org/CVERecord?id=CVE-2019-0154"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2019-0154",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2019-0154"
},
{
"category": "external",
"summary": "https://access.redhat.com/solutions/i915-graphics",
"url": "https://access.redhat.com/solutions/i915-graphics"
},
{
"category": "external",
"summary": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00260.html",
"url": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00260.html"
}
],
"release_date": "2019-11-12T18:00:00+00:00",
"remediations": [
{
"category": "vendor_fix",
"date": "2019-11-12T21:37:14+00:00",
"details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/11258\n\nThe system must be rebooted for this update to take effect.",
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],
"restart_required": {
"category": "machine"
},
"url": "https://access.redhat.com/errata/RHSA-2019:3839"
},
{
"category": "workaround",
"details": "Preventing loading of the i915 kernel module will prevent attackers from using this exploit against the system however the power management functionality of the card will be disabled and the system may draw additional power. See this KCS article (https://access.redhat.com/solutions/41278) for instructions on how to disable a kernel module. Graphical displays may also be at low resolution or not work correctly. This mitigation may not be suitable if running graphical tools locally is required.",
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}
],
"scores": [
{
"cvss_v3": {
"attackComplexity": "LOW",
"attackVector": "LOCAL",
"availabilityImpact": "HIGH",
"baseScore": 6.5,
"baseSeverity": "MEDIUM",
"confidentialityImpact": "NONE",
"integrityImpact": "NONE",
"privilegesRequired": "LOW",
"scope": "CHANGED",
"userInteraction": "NONE",
"vectorString": "CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:N/I:N/A:H",
"version": "3.0"
},
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}
],
"threats": [
{
"category": "impact",
"details": "Moderate"
}
],
"title": "hw: Intel GPU Denial Of Service while accessing MMIO in lower power state"
},
{
"acknowledgments": [
{
"names": [
"Intel"
]
}
],
"cve": "CVE-2019-11135",
"cwe": {
"id": "CWE-203",
"name": "Observable Discrepancy"
},
"discovery_date": "2019-09-18T00:00:00+00:00",
"ids": [
{
"system_name": "Red Hat Bugzilla ID",
"text": "1753062"
}
],
"notes": [
{
"category": "description",
"text": "A flaw was found in the way Intel CPUs handle speculative execution of instructions when the TSX Asynchronous Abort (TAA) error occurs. A local authenticated attacker with the ability to monitor execution times could infer the TSX memory state by comparing abort execution times. This could allow information disclosure via this observed side-channel for any TSX transaction being executed while an attacker is able to observe abort timing.\r\n\r\nIntel\u0027s Transactional Synchronisation Extensions (TSX) are set of instructions which enable transactional memory support to improve performance of the multi-threaded applications, in the lock-protected critical sections. The CPU executes instructions in the critical-sections as transactions, while ensuring their atomic state. When such transaction execution is unsuccessful, the processor cannot ensure atomic updates to the transaction memory, so the processor rolls back or aborts such transaction execution.\r\n\r\nWhile TSX Asynchronous Abort (TAA) is pending, CPU may continue to read data from architectural buffers and pass it to the dependent speculative operations. This may cause information leakage via speculative side-channel means, which is quite similar to the Microarchitectural Data Sampling (MDS) issue.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "hw: TSX Transaction Asynchronous Abort (TAA)",
"title": "Vulnerability summary"
},
{
"category": "other",
"text": "libvirt and qemu-kvm on Red Hat Enterprise Linux 6 are not affected by this vulnerability as they do not support MSR-based CPU features.",
"title": "Statement"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
],
"product_status": {
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},
"references": [
{
"category": "self",
"summary": "Canonical URL",
"url": "https://access.redhat.com/security/cve/CVE-2019-11135"
},
{
"category": "external",
"summary": "RHBZ#1753062",
"url": "https://bugzilla.redhat.com/show_bug.cgi?id=1753062"
},
{
"category": "external",
"summary": "https://www.cve.org/CVERecord?id=CVE-2019-11135",
"url": "https://www.cve.org/CVERecord?id=CVE-2019-11135"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2019-11135",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2019-11135"
},
{
"category": "external",
"summary": "https://access.redhat.com/solutions/tsx-asynchronousabort",
"url": "https://access.redhat.com/solutions/tsx-asynchronousabort"
},
{
"category": "external",
"summary": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00270.html",
"url": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00270.html"
}
],
"release_date": "2019-11-12T18:00:00+00:00",
"remediations": [
{
"category": "vendor_fix",
"date": "2019-11-12T21:37:14+00:00",
"details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/11258\n\nThe system must be rebooted for this update to take effect.",
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"url": "https://access.redhat.com/errata/RHSA-2019:3839"
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}
],
"scores": [
{
"cvss_v3": {
"attackComplexity": "LOW",
"attackVector": "LOCAL",
"availabilityImpact": "NONE",
"baseScore": 6.5,
"baseSeverity": "MEDIUM",
"confidentialityImpact": "HIGH",
"integrityImpact": "NONE",
"privilegesRequired": "LOW",
"scope": "CHANGED",
"userInteraction": "NONE",
"vectorString": "CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:N/A:N",
"version": "3.0"
},
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]
}
],
"threats": [
{
"category": "impact",
"details": "Moderate"
}
],
"title": "hw: TSX Transaction Asynchronous Abort (TAA)"
}
]
}
RHSA-2019_3840
Vulnerability from csaf_redhat - Published: 2019-11-12 21:22 - Updated: 2024-11-15 03:17A flaw was found in the way Intel CPUs handle inconsistency between, virtual to physical memory address translations in CPU's local cache and system software's Paging structure entries. A privileged guest user may use this flaw to induce a hardware Machine Check Error on the host processor, resulting in a severe DoS scenario by halting the processor. System software like OS OR Virtual Machine Monitor (VMM) use virtual memory system for storing program instructions and data in memory. Virtual Memory system uses Paging structures like Page Tables and Page Directories to manage system memory. The processor's Memory Management Unit (MMU) uses Paging structure entries to translate program's virtual memory addresses to physical memory addresses. The processor stores these address translations into its local cache buffer called - Translation Lookaside Buffer (TLB). TLB has two parts, one for instructions and other for data addresses. System software can modify its Paging structure entries to change address mappings OR certain attributes like page size etc. Upon such Paging structure alterations in memory, system software must invalidate the corresponding address translations in the processor's TLB cache. But before this TLB invalidation takes place, a privileged guest user may trigger an instruction fetch operation, which could use an already cached, but now invalid, virtual to physical address translation from Instruction TLB (ITLB). Thus accessing an invalid physical memory address and resulting in halting the processor due to the Machine Check Error (MCE) on Page Size Change.
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| Unresolved product id: 7Server-7.3.AUS:kernel-tools-0:3.10.0-514.70.2.el7.x86_64 | — |
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| Unresolved product id: 7Server-7.3.E4S:kernel-0:3.10.0-514.70.2.el7.ppc64le | — |
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A flaw was found in Intel graphics hardware (GPU) where a local attacker with the ability to issue an ioctl could trigger a hardware level crash if MMIO registers were read while the graphics card was in a low-power state. This creates a denial of service situation and the GPU and connected displays will remain unusable until a reboot occurs.
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A flaw was found in the way Intel CPUs handle speculative execution of instructions when the TSX Asynchronous Abort (TAA) error occurs. A local authenticated attacker with the ability to monitor execution times could infer the TSX memory state by comparing abort execution times. This could allow information disclosure via this observed side-channel for any TSX transaction being executed while an attacker is able to observe abort timing. Intel's Transactional Synchronisation Extensions (TSX) are set of instructions which enable transactional memory support to improve performance of the multi-threaded applications, in the lock-protected critical sections. The CPU executes instructions in the critical-sections as transactions, while ensuring their atomic state. When such transaction execution is unsuccessful, the processor cannot ensure atomic updates to the transaction memory, so the processor rolls back or aborts such transaction execution. While TSX Asynchronous Abort (TAA) is pending, CPU may continue to read data from architectural buffers and pass it to the dependent speculative operations. This may cause information leakage via speculative side-channel means, which is quite similar to the Microarchitectural Data Sampling (MDS) issue.
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{
"acknowledgments": [
{
"names": [
"Intel"
]
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{
"names": [
"Deepak Gupta"
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"summary": "Acknowledged by upstream."
}
],
"cve": "CVE-2018-12207",
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"id": "CWE-226",
"name": "Sensitive Information in Resource Not Removed Before Reuse"
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"discovery_date": "2018-11-06T00:00:00+00:00",
"ids": [
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"system_name": "Red Hat Bugzilla ID",
"text": "1646768"
}
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{
"category": "description",
"text": "A flaw was found in the way Intel CPUs handle inconsistency between, virtual to physical memory address translations in CPU\u0027s local cache and system software\u0027s Paging structure entries. A privileged guest user may use this flaw to induce a hardware Machine Check Error on the host processor, resulting in a severe DoS scenario by halting the processor.\r\n\r\nSystem software like OS OR Virtual Machine Monitor (VMM) use virtual memory system for storing program instructions and data in memory. Virtual Memory system uses Paging structures like Page Tables and Page Directories to manage system memory. The processor\u0027s Memory Management Unit (MMU) uses Paging structure entries to translate program\u0027s virtual memory addresses to physical memory addresses. The processor stores these address translations into its local cache buffer called - Translation Lookaside Buffer (TLB). TLB has two parts, one for instructions and other for data addresses.\r\n\r\nSystem software can modify its Paging structure entries to change address mappings OR certain attributes like page size etc. Upon such Paging structure alterations in memory, system software must invalidate the corresponding address translations in the processor\u0027s TLB cache. But before this TLB invalidation takes place, a privileged guest user may trigger an instruction fetch operation, which could use an already cached, but now invalid, virtual to physical address translation from Instruction TLB (ITLB). Thus accessing an invalid physical memory address and resulting in halting the processor due to the Machine Check Error (MCE) on Page Size Change.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "hw: Machine Check Error on Page Size Change (IFU)",
"title": "Vulnerability summary"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
],
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},
"references": [
{
"category": "self",
"summary": "Canonical URL",
"url": "https://access.redhat.com/security/cve/CVE-2018-12207"
},
{
"category": "external",
"summary": "RHBZ#1646768",
"url": "https://bugzilla.redhat.com/show_bug.cgi?id=1646768"
},
{
"category": "external",
"summary": "RHSB-ifu-page-mce",
"url": "https://access.redhat.com/security/vulnerabilities/ifu-page-mce"
},
{
"category": "external",
"summary": "https://www.cve.org/CVERecord?id=CVE-2018-12207",
"url": "https://www.cve.org/CVERecord?id=CVE-2018-12207"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2018-12207",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2018-12207"
},
{
"category": "external",
"summary": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00210.html",
"url": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00210.html"
}
],
"release_date": "2019-11-12T18:00:00+00:00",
"remediations": [
{
"category": "vendor_fix",
"date": "2019-11-12T21:22:53+00:00",
"details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/11258\n\nThe system must be rebooted for this update to take effect.",
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],
"restart_required": {
"category": "machine"
},
"url": "https://access.redhat.com/errata/RHSA-2019:3840"
},
{
"category": "workaround",
"details": "For mitigation related information, please refer to the Red Hat vulnerability article: https://access.redhat.com/security/vulnerabilities/ifu-page-mce .",
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],
"scores": [
{
"cvss_v3": {
"attackComplexity": "LOW",
"attackVector": "LOCAL",
"availabilityImpact": "HIGH",
"baseScore": 6.5,
"baseSeverity": "MEDIUM",
"confidentialityImpact": "NONE",
"integrityImpact": "NONE",
"privilegesRequired": "LOW",
"scope": "CHANGED",
"userInteraction": "NONE",
"vectorString": "CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:N/I:N/A:H",
"version": "3.0"
},
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],
"threats": [
{
"category": "impact",
"details": "Important"
}
],
"title": "hw: Machine Check Error on Page Size Change (IFU)"
},
{
"acknowledgments": [
{
"names": [
"Intel"
]
}
],
"cve": "CVE-2019-0154",
"cwe": {
"id": "CWE-284",
"name": "Improper Access Control"
},
"discovery_date": "2019-06-27T00:00:00+00:00",
"ids": [
{
"system_name": "Red Hat Bugzilla ID",
"text": "1724393"
}
],
"notes": [
{
"category": "description",
"text": "A flaw was found in Intel graphics hardware (GPU) where a local attacker with the ability to issue an ioctl could trigger a hardware level crash if MMIO registers were read while the graphics card was in a low-power state. This creates a denial of service situation and the GPU and connected displays will remain unusable until a reboot occurs.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "hw: Intel GPU Denial Of Service while accessing MMIO in lower power state",
"title": "Vulnerability summary"
},
{
"category": "other",
"text": "Intel plans to release BIOS firmware to correct this issue. Red Hat\u0027s kernel update should mitigate this vulnerability. Some older hardware will not have BIOS firmware update and will rely on operating system level protection to prevent access while the device is in low-power states. For more information see https://access.redhat.com/solutions/i915-graphics",
"title": "Statement"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
],
"product_status": {
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},
"references": [
{
"category": "self",
"summary": "Canonical URL",
"url": "https://access.redhat.com/security/cve/CVE-2019-0154"
},
{
"category": "external",
"summary": "RHBZ#1724393",
"url": "https://bugzilla.redhat.com/show_bug.cgi?id=1724393"
},
{
"category": "external",
"summary": "https://www.cve.org/CVERecord?id=CVE-2019-0154",
"url": "https://www.cve.org/CVERecord?id=CVE-2019-0154"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2019-0154",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2019-0154"
},
{
"category": "external",
"summary": "https://access.redhat.com/solutions/i915-graphics",
"url": "https://access.redhat.com/solutions/i915-graphics"
},
{
"category": "external",
"summary": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00260.html",
"url": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00260.html"
}
],
"release_date": "2019-11-12T18:00:00+00:00",
"remediations": [
{
"category": "vendor_fix",
"date": "2019-11-12T21:22:53+00:00",
"details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/11258\n\nThe system must be rebooted for this update to take effect.",
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],
"restart_required": {
"category": "machine"
},
"url": "https://access.redhat.com/errata/RHSA-2019:3840"
},
{
"category": "workaround",
"details": "Preventing loading of the i915 kernel module will prevent attackers from using this exploit against the system however the power management functionality of the card will be disabled and the system may draw additional power. See this KCS article (https://access.redhat.com/solutions/41278) for instructions on how to disable a kernel module. Graphical displays may also be at low resolution or not work correctly. This mitigation may not be suitable if running graphical tools locally is required.",
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}
],
"scores": [
{
"cvss_v3": {
"attackComplexity": "LOW",
"attackVector": "LOCAL",
"availabilityImpact": "HIGH",
"baseScore": 6.5,
"baseSeverity": "MEDIUM",
"confidentialityImpact": "NONE",
"integrityImpact": "NONE",
"privilegesRequired": "LOW",
"scope": "CHANGED",
"userInteraction": "NONE",
"vectorString": "CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:N/I:N/A:H",
"version": "3.0"
},
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}
],
"threats": [
{
"category": "impact",
"details": "Moderate"
}
],
"title": "hw: Intel GPU Denial Of Service while accessing MMIO in lower power state"
},
{
"acknowledgments": [
{
"names": [
"Intel"
]
}
],
"cve": "CVE-2019-11135",
"cwe": {
"id": "CWE-203",
"name": "Observable Discrepancy"
},
"discovery_date": "2019-09-18T00:00:00+00:00",
"ids": [
{
"system_name": "Red Hat Bugzilla ID",
"text": "1753062"
}
],
"notes": [
{
"category": "description",
"text": "A flaw was found in the way Intel CPUs handle speculative execution of instructions when the TSX Asynchronous Abort (TAA) error occurs. A local authenticated attacker with the ability to monitor execution times could infer the TSX memory state by comparing abort execution times. This could allow information disclosure via this observed side-channel for any TSX transaction being executed while an attacker is able to observe abort timing.\r\n\r\nIntel\u0027s Transactional Synchronisation Extensions (TSX) are set of instructions which enable transactional memory support to improve performance of the multi-threaded applications, in the lock-protected critical sections. The CPU executes instructions in the critical-sections as transactions, while ensuring their atomic state. When such transaction execution is unsuccessful, the processor cannot ensure atomic updates to the transaction memory, so the processor rolls back or aborts such transaction execution.\r\n\r\nWhile TSX Asynchronous Abort (TAA) is pending, CPU may continue to read data from architectural buffers and pass it to the dependent speculative operations. This may cause information leakage via speculative side-channel means, which is quite similar to the Microarchitectural Data Sampling (MDS) issue.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "hw: TSX Transaction Asynchronous Abort (TAA)",
"title": "Vulnerability summary"
},
{
"category": "other",
"text": "libvirt and qemu-kvm on Red Hat Enterprise Linux 6 are not affected by this vulnerability as they do not support MSR-based CPU features.",
"title": "Statement"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
],
"product_status": {
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},
"references": [
{
"category": "self",
"summary": "Canonical URL",
"url": "https://access.redhat.com/security/cve/CVE-2019-11135"
},
{
"category": "external",
"summary": "RHBZ#1753062",
"url": "https://bugzilla.redhat.com/show_bug.cgi?id=1753062"
},
{
"category": "external",
"summary": "https://www.cve.org/CVERecord?id=CVE-2019-11135",
"url": "https://www.cve.org/CVERecord?id=CVE-2019-11135"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2019-11135",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2019-11135"
},
{
"category": "external",
"summary": "https://access.redhat.com/solutions/tsx-asynchronousabort",
"url": "https://access.redhat.com/solutions/tsx-asynchronousabort"
},
{
"category": "external",
"summary": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00270.html",
"url": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00270.html"
}
],
"release_date": "2019-11-12T18:00:00+00:00",
"remediations": [
{
"category": "vendor_fix",
"date": "2019-11-12T21:22:53+00:00",
"details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/11258\n\nThe system must be rebooted for this update to take effect.",
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"url": "https://access.redhat.com/errata/RHSA-2019:3840"
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{
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}
],
"scores": [
{
"cvss_v3": {
"attackComplexity": "LOW",
"attackVector": "LOCAL",
"availabilityImpact": "NONE",
"baseScore": 6.5,
"baseSeverity": "MEDIUM",
"confidentialityImpact": "HIGH",
"integrityImpact": "NONE",
"privilegesRequired": "LOW",
"scope": "CHANGED",
"userInteraction": "NONE",
"vectorString": "CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:N/A:N",
"version": "3.0"
},
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]
}
],
"threats": [
{
"category": "impact",
"details": "Moderate"
}
],
"title": "hw: TSX Transaction Asynchronous Abort (TAA)"
}
]
}
RHSA-2019_3841
Vulnerability from csaf_redhat - Published: 2019-11-12 21:02 - Updated: 2024-11-15 03:17A flaw was found in the way Intel CPUs handle inconsistency between, virtual to physical memory address translations in CPU's local cache and system software's Paging structure entries. A privileged guest user may use this flaw to induce a hardware Machine Check Error on the host processor, resulting in a severe DoS scenario by halting the processor. System software like OS OR Virtual Machine Monitor (VMM) use virtual memory system for storing program instructions and data in memory. Virtual Memory system uses Paging structures like Page Tables and Page Directories to manage system memory. The processor's Memory Management Unit (MMU) uses Paging structure entries to translate program's virtual memory addresses to physical memory addresses. The processor stores these address translations into its local cache buffer called - Translation Lookaside Buffer (TLB). TLB has two parts, one for instructions and other for data addresses. System software can modify its Paging structure entries to change address mappings OR certain attributes like page size etc. Upon such Paging structure alterations in memory, system software must invalidate the corresponding address translations in the processor's TLB cache. But before this TLB invalidation takes place, a privileged guest user may trigger an instruction fetch operation, which could use an already cached, but now invalid, virtual to physical address translation from Instruction TLB (ITLB). Thus accessing an invalid physical memory address and resulting in halting the processor due to the Machine Check Error (MCE) on Page Size Change.
| Product | Identifier | Version | Remediation |
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A flaw was found in Intel graphics hardware (GPU) where a local attacker with the ability to issue an ioctl could trigger a hardware level crash if MMIO registers were read while the graphics card was in a low-power state. This creates a denial of service situation and the GPU and connected displays will remain unusable until a reboot occurs.
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A flaw was found in the Intel graphics hardware (GPU), where a local attacker with the ability to issue commands to the GPU could inadvertently lead to memory corruption and possible privilege escalation. The attacker could use the GPU blitter to perform privilege MMIO operations, not limited to the address space required to function correctly.
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A flaw was found in the way Intel CPUs handle speculative execution of instructions when the TSX Asynchronous Abort (TAA) error occurs. A local authenticated attacker with the ability to monitor execution times could infer the TSX memory state by comparing abort execution times. This could allow information disclosure via this observed side-channel for any TSX transaction being executed while an attacker is able to observe abort timing. Intel's Transactional Synchronisation Extensions (TSX) are set of instructions which enable transactional memory support to improve performance of the multi-threaded applications, in the lock-protected critical sections. The CPU executes instructions in the critical-sections as transactions, while ensuring their atomic state. When such transaction execution is unsuccessful, the processor cannot ensure atomic updates to the transaction memory, so the processor rolls back or aborts such transaction execution. While TSX Asynchronous Abort (TAA) is pending, CPU may continue to read data from architectural buffers and pass it to the dependent speculative operations. This may cause information leakage via speculative side-channel means, which is quite similar to the Microarchitectural Data Sampling (MDS) issue.
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"acknowledgments": [
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"names": [
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"names": [
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"summary": "Acknowledged by upstream."
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"name": "Sensitive Information in Resource Not Removed Before Reuse"
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"discovery_date": "2018-11-06T00:00:00+00:00",
"ids": [
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"text": "1646768"
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{
"category": "description",
"text": "A flaw was found in the way Intel CPUs handle inconsistency between, virtual to physical memory address translations in CPU\u0027s local cache and system software\u0027s Paging structure entries. A privileged guest user may use this flaw to induce a hardware Machine Check Error on the host processor, resulting in a severe DoS scenario by halting the processor.\r\n\r\nSystem software like OS OR Virtual Machine Monitor (VMM) use virtual memory system for storing program instructions and data in memory. Virtual Memory system uses Paging structures like Page Tables and Page Directories to manage system memory. The processor\u0027s Memory Management Unit (MMU) uses Paging structure entries to translate program\u0027s virtual memory addresses to physical memory addresses. The processor stores these address translations into its local cache buffer called - Translation Lookaside Buffer (TLB). TLB has two parts, one for instructions and other for data addresses.\r\n\r\nSystem software can modify its Paging structure entries to change address mappings OR certain attributes like page size etc. Upon such Paging structure alterations in memory, system software must invalidate the corresponding address translations in the processor\u0027s TLB cache. But before this TLB invalidation takes place, a privileged guest user may trigger an instruction fetch operation, which could use an already cached, but now invalid, virtual to physical address translation from Instruction TLB (ITLB). Thus accessing an invalid physical memory address and resulting in halting the processor due to the Machine Check Error (MCE) on Page Size Change.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "hw: Machine Check Error on Page Size Change (IFU)",
"title": "Vulnerability summary"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
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},
"references": [
{
"category": "self",
"summary": "Canonical URL",
"url": "https://access.redhat.com/security/cve/CVE-2018-12207"
},
{
"category": "external",
"summary": "RHBZ#1646768",
"url": "https://bugzilla.redhat.com/show_bug.cgi?id=1646768"
},
{
"category": "external",
"summary": "RHSB-ifu-page-mce",
"url": "https://access.redhat.com/security/vulnerabilities/ifu-page-mce"
},
{
"category": "external",
"summary": "https://www.cve.org/CVERecord?id=CVE-2018-12207",
"url": "https://www.cve.org/CVERecord?id=CVE-2018-12207"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2018-12207",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2018-12207"
},
{
"category": "external",
"summary": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00210.html",
"url": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00210.html"
}
],
"release_date": "2019-11-12T18:00:00+00:00",
"remediations": [
{
"category": "vendor_fix",
"date": "2019-11-12T21:02:11+00:00",
"details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/11258\n\nThe system must be rebooted for this update to take effect.",
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"restart_required": {
"category": "machine"
},
"url": "https://access.redhat.com/errata/RHSA-2019:3841"
},
{
"category": "workaround",
"details": "For mitigation related information, please refer to the Red Hat vulnerability article: https://access.redhat.com/security/vulnerabilities/ifu-page-mce .",
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}
],
"scores": [
{
"cvss_v3": {
"attackComplexity": "LOW",
"attackVector": "LOCAL",
"availabilityImpact": "HIGH",
"baseScore": 6.5,
"baseSeverity": "MEDIUM",
"confidentialityImpact": "NONE",
"integrityImpact": "NONE",
"privilegesRequired": "LOW",
"scope": "CHANGED",
"userInteraction": "NONE",
"vectorString": "CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:N/I:N/A:H",
"version": "3.0"
},
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],
"threats": [
{
"category": "impact",
"details": "Important"
}
],
"title": "hw: Machine Check Error on Page Size Change (IFU)"
},
{
"acknowledgments": [
{
"names": [
"Intel"
]
}
],
"cve": "CVE-2019-0154",
"cwe": {
"id": "CWE-284",
"name": "Improper Access Control"
},
"discovery_date": "2019-06-27T00:00:00+00:00",
"ids": [
{
"system_name": "Red Hat Bugzilla ID",
"text": "1724393"
}
],
"notes": [
{
"category": "description",
"text": "A flaw was found in Intel graphics hardware (GPU) where a local attacker with the ability to issue an ioctl could trigger a hardware level crash if MMIO registers were read while the graphics card was in a low-power state. This creates a denial of service situation and the GPU and connected displays will remain unusable until a reboot occurs.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "hw: Intel GPU Denial Of Service while accessing MMIO in lower power state",
"title": "Vulnerability summary"
},
{
"category": "other",
"text": "Intel plans to release BIOS firmware to correct this issue. Red Hat\u0027s kernel update should mitigate this vulnerability. Some older hardware will not have BIOS firmware update and will rely on operating system level protection to prevent access while the device is in low-power states. For more information see https://access.redhat.com/solutions/i915-graphics",
"title": "Statement"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
],
"product_status": {
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},
"references": [
{
"category": "self",
"summary": "Canonical URL",
"url": "https://access.redhat.com/security/cve/CVE-2019-0154"
},
{
"category": "external",
"summary": "RHBZ#1724393",
"url": "https://bugzilla.redhat.com/show_bug.cgi?id=1724393"
},
{
"category": "external",
"summary": "https://www.cve.org/CVERecord?id=CVE-2019-0154",
"url": "https://www.cve.org/CVERecord?id=CVE-2019-0154"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2019-0154",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2019-0154"
},
{
"category": "external",
"summary": "https://access.redhat.com/solutions/i915-graphics",
"url": "https://access.redhat.com/solutions/i915-graphics"
},
{
"category": "external",
"summary": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00260.html",
"url": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00260.html"
}
],
"release_date": "2019-11-12T18:00:00+00:00",
"remediations": [
{
"category": "vendor_fix",
"date": "2019-11-12T21:02:11+00:00",
"details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/11258\n\nThe system must be rebooted for this update to take effect.",
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],
"restart_required": {
"category": "machine"
},
"url": "https://access.redhat.com/errata/RHSA-2019:3841"
},
{
"category": "workaround",
"details": "Preventing loading of the i915 kernel module will prevent attackers from using this exploit against the system however the power management functionality of the card will be disabled and the system may draw additional power. See this KCS article (https://access.redhat.com/solutions/41278) for instructions on how to disable a kernel module. Graphical displays may also be at low resolution or not work correctly. This mitigation may not be suitable if running graphical tools locally is required.",
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{
"cvss_v3": {
"attackComplexity": "LOW",
"attackVector": "LOCAL",
"availabilityImpact": "HIGH",
"baseScore": 6.5,
"baseSeverity": "MEDIUM",
"confidentialityImpact": "NONE",
"integrityImpact": "NONE",
"privilegesRequired": "LOW",
"scope": "CHANGED",
"userInteraction": "NONE",
"vectorString": "CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:N/I:N/A:H",
"version": "3.0"
},
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}
],
"threats": [
{
"category": "impact",
"details": "Moderate"
}
],
"title": "hw: Intel GPU Denial Of Service while accessing MMIO in lower power state"
},
{
"acknowledgments": [
{
"names": [
"Intel"
]
}
],
"cve": "CVE-2019-0155",
"cwe": {
"id": "CWE-284",
"name": "Improper Access Control"
},
"discovery_date": "2019-06-27T00:00:00+00:00",
"ids": [
{
"system_name": "Red Hat Bugzilla ID",
"text": "1724398"
}
],
"notes": [
{
"category": "description",
"text": "A flaw was found in the Intel graphics hardware (GPU), where a local attacker with the ability to issue commands to the GPU could inadvertently lead to memory corruption and possible privilege escalation. The attacker could use the GPU blitter to perform privilege MMIO operations, not limited to the address space required to function correctly.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "hw: Intel GPU blitter manipulation can allow for arbitrary kernel memory write",
"title": "Vulnerability summary"
},
{
"category": "other",
"text": "Red Hat Product Security is aware of this issue. Updates will be released as they become available. For additional information, please refer to the Red Hat Knowledgebase article: https://access.redhat.com/solutions/i915-graphics",
"title": "Statement"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
],
"product_status": {
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},
"references": [
{
"category": "self",
"summary": "Canonical URL",
"url": "https://access.redhat.com/security/cve/CVE-2019-0155"
},
{
"category": "external",
"summary": "RHBZ#1724398",
"url": "https://bugzilla.redhat.com/show_bug.cgi?id=1724398"
},
{
"category": "external",
"summary": "https://www.cve.org/CVERecord?id=CVE-2019-0155",
"url": "https://www.cve.org/CVERecord?id=CVE-2019-0155"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2019-0155",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2019-0155"
},
{
"category": "external",
"summary": "https://access.redhat.com/solutions/i915-graphics",
"url": "https://access.redhat.com/solutions/i915-graphics"
},
{
"category": "external",
"summary": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00242.html",
"url": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00242.html"
}
],
"release_date": "2019-11-12T18:00:00+00:00",
"remediations": [
{
"category": "vendor_fix",
"date": "2019-11-12T21:02:11+00:00",
"details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/11258\n\nThe system must be rebooted for this update to take effect.",
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],
"restart_required": {
"category": "machine"
},
"url": "https://access.redhat.com/errata/RHSA-2019:3841"
},
{
"category": "workaround",
"details": "Preventing loading of the i915 kernel module will prevent attackers from using this exploit against the system however the power management functionality of the card will be disabled and the system may draw additional power. See this KCS article( https://access.redhat.com/solutions/41278 ) for instructions on how to disable a kernel module. Graphical displays may also be at low resolution or not work correctly. This mitigation may not be suitable if running graphical tools locally is required.",
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}
],
"scores": [
{
"cvss_v3": {
"attackComplexity": "LOW",
"attackVector": "LOCAL",
"availabilityImpact": "HIGH",
"baseScore": 8.8,
"baseSeverity": "HIGH",
"confidentialityImpact": "HIGH",
"integrityImpact": "HIGH",
"privilegesRequired": "LOW",
"scope": "CHANGED",
"userInteraction": "NONE",
"vectorString": "CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:H/A:H",
"version": "3.0"
},
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],
"threats": [
{
"category": "impact",
"details": "Important"
}
],
"title": "hw: Intel GPU blitter manipulation can allow for arbitrary kernel memory write"
},
{
"acknowledgments": [
{
"names": [
"Intel"
]
}
],
"cve": "CVE-2019-11135",
"cwe": {
"id": "CWE-203",
"name": "Observable Discrepancy"
},
"discovery_date": "2019-09-18T00:00:00+00:00",
"ids": [
{
"system_name": "Red Hat Bugzilla ID",
"text": "1753062"
}
],
"notes": [
{
"category": "description",
"text": "A flaw was found in the way Intel CPUs handle speculative execution of instructions when the TSX Asynchronous Abort (TAA) error occurs. A local authenticated attacker with the ability to monitor execution times could infer the TSX memory state by comparing abort execution times. This could allow information disclosure via this observed side-channel for any TSX transaction being executed while an attacker is able to observe abort timing.\r\n\r\nIntel\u0027s Transactional Synchronisation Extensions (TSX) are set of instructions which enable transactional memory support to improve performance of the multi-threaded applications, in the lock-protected critical sections. The CPU executes instructions in the critical-sections as transactions, while ensuring their atomic state. When such transaction execution is unsuccessful, the processor cannot ensure atomic updates to the transaction memory, so the processor rolls back or aborts such transaction execution.\r\n\r\nWhile TSX Asynchronous Abort (TAA) is pending, CPU may continue to read data from architectural buffers and pass it to the dependent speculative operations. This may cause information leakage via speculative side-channel means, which is quite similar to the Microarchitectural Data Sampling (MDS) issue.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "hw: TSX Transaction Asynchronous Abort (TAA)",
"title": "Vulnerability summary"
},
{
"category": "other",
"text": "libvirt and qemu-kvm on Red Hat Enterprise Linux 6 are not affected by this vulnerability as they do not support MSR-based CPU features.",
"title": "Statement"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
],
"product_status": {
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},
"references": [
{
"category": "self",
"summary": "Canonical URL",
"url": "https://access.redhat.com/security/cve/CVE-2019-11135"
},
{
"category": "external",
"summary": "RHBZ#1753062",
"url": "https://bugzilla.redhat.com/show_bug.cgi?id=1753062"
},
{
"category": "external",
"summary": "https://www.cve.org/CVERecord?id=CVE-2019-11135",
"url": "https://www.cve.org/CVERecord?id=CVE-2019-11135"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2019-11135",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2019-11135"
},
{
"category": "external",
"summary": "https://access.redhat.com/solutions/tsx-asynchronousabort",
"url": "https://access.redhat.com/solutions/tsx-asynchronousabort"
},
{
"category": "external",
"summary": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00270.html",
"url": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00270.html"
}
],
"release_date": "2019-11-12T18:00:00+00:00",
"remediations": [
{
"category": "vendor_fix",
"date": "2019-11-12T21:02:11+00:00",
"details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/11258\n\nThe system must be rebooted for this update to take effect.",
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],
"restart_required": {
"category": "machine"
},
"url": "https://access.redhat.com/errata/RHSA-2019:3841"
},
{
"category": "workaround",
"details": "For mitigation related information, please refer to the Red Hat Knowledgebase article: https://access.redhat.com/solutions/tsx-asynchronousabort",
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],
"scores": [
{
"cvss_v3": {
"attackComplexity": "LOW",
"attackVector": "LOCAL",
"availabilityImpact": "NONE",
"baseScore": 6.5,
"baseSeverity": "MEDIUM",
"confidentialityImpact": "HIGH",
"integrityImpact": "NONE",
"privilegesRequired": "LOW",
"scope": "CHANGED",
"userInteraction": "NONE",
"vectorString": "CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:N/A:N",
"version": "3.0"
},
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}
],
"threats": [
{
"category": "impact",
"details": "Moderate"
}
],
"title": "hw: TSX Transaction Asynchronous Abort (TAA)"
}
]
}
RHSA-2019_3842
Vulnerability from csaf_redhat - Published: 2019-11-12 21:11 - Updated: 2024-11-15 03:17A flaw was found in the way Intel CPUs handle inconsistency between, virtual to physical memory address translations in CPU's local cache and system software's Paging structure entries. A privileged guest user may use this flaw to induce a hardware Machine Check Error on the host processor, resulting in a severe DoS scenario by halting the processor. System software like OS OR Virtual Machine Monitor (VMM) use virtual memory system for storing program instructions and data in memory. Virtual Memory system uses Paging structures like Page Tables and Page Directories to manage system memory. The processor's Memory Management Unit (MMU) uses Paging structure entries to translate program's virtual memory addresses to physical memory addresses. The processor stores these address translations into its local cache buffer called - Translation Lookaside Buffer (TLB). TLB has two parts, one for instructions and other for data addresses. System software can modify its Paging structure entries to change address mappings OR certain attributes like page size etc. Upon such Paging structure alterations in memory, system software must invalidate the corresponding address translations in the processor's TLB cache. But before this TLB invalidation takes place, a privileged guest user may trigger an instruction fetch operation, which could use an already cached, but now invalid, virtual to physical address translation from Instruction TLB (ITLB). Thus accessing an invalid physical memory address and resulting in halting the processor due to the Machine Check Error (MCE) on Page Size Change.
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|---|---|---|---|
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| Unresolved product id: 6Server-6.6.AUS:kernel-debug-debuginfo-0:2.6.32-504.81.3.el6.x86_64 | — |
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| Unresolved product id: 6Server-6.6.AUS:kernel-debug-devel-0:2.6.32-504.81.3.el6.x86_64 | — |
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| Unresolved product id: 6Server-6.6.AUS:kernel-debuginfo-0:2.6.32-504.81.3.el6.x86_64 | — |
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| Unresolved product id: 6Server-6.6.AUS:kernel-debuginfo-common-x86_64-0:2.6.32-504.81.3.el6.x86_64 | — |
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| Unresolved product id: 6Server-6.6.AUS:kernel-devel-0:2.6.32-504.81.3.el6.x86_64 | — |
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| Unresolved product id: 6Server-6.6.AUS:kernel-doc-0:2.6.32-504.81.3.el6.noarch | — |
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| Unresolved product id: 6Server-6.6.AUS:python-perf-debuginfo-0:2.6.32-504.81.3.el6.x86_64 | — |
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| Unresolved product id: 6Server-optional-6.6.AUS:kernel-0:2.6.32-504.81.3.el6.src | — |
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| Unresolved product id: 6Server-optional-6.6.AUS:kernel-0:2.6.32-504.81.3.el6.x86_64 | — |
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| Unresolved product id: 6Server-optional-6.6.AUS:kernel-debug-0:2.6.32-504.81.3.el6.x86_64 | — |
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| Unresolved product id: 6Server-optional-6.6.AUS:kernel-debug-debuginfo-0:2.6.32-504.81.3.el6.x86_64 | — |
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| Unresolved product id: 6Server-optional-6.6.AUS:kernel-debug-devel-0:2.6.32-504.81.3.el6.x86_64 | — |
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| Unresolved product id: 6Server-optional-6.6.AUS:kernel-debuginfo-common-x86_64-0:2.6.32-504.81.3.el6.x86_64 | — |
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A flaw was found in the way Intel CPUs handle speculative execution of instructions when the TSX Asynchronous Abort (TAA) error occurs. A local authenticated attacker with the ability to monitor execution times could infer the TSX memory state by comparing abort execution times. This could allow information disclosure via this observed side-channel for any TSX transaction being executed while an attacker is able to observe abort timing. Intel's Transactional Synchronisation Extensions (TSX) are set of instructions which enable transactional memory support to improve performance of the multi-threaded applications, in the lock-protected critical sections. The CPU executes instructions in the critical-sections as transactions, while ensuring their atomic state. When such transaction execution is unsuccessful, the processor cannot ensure atomic updates to the transaction memory, so the processor rolls back or aborts such transaction execution. While TSX Asynchronous Abort (TAA) is pending, CPU may continue to read data from architectural buffers and pass it to the dependent speculative operations. This may cause information leakage via speculative side-channel means, which is quite similar to the Microarchitectural Data Sampling (MDS) issue.
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| Unresolved product id: 6Server-6.6.AUS:kernel-0:2.6.32-504.81.3.el6.src | — |
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| Unresolved product id: 6Server-6.6.AUS:kernel-abi-whitelists-0:2.6.32-504.81.3.el6.noarch | — |
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| Unresolved product id: 6Server-6.6.AUS:kernel-debug-0:2.6.32-504.81.3.el6.x86_64 | — |
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| Unresolved product id: 6Server-6.6.AUS:kernel-debug-debuginfo-0:2.6.32-504.81.3.el6.x86_64 | — |
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| Unresolved product id: 6Server-6.6.AUS:kernel-debug-devel-0:2.6.32-504.81.3.el6.x86_64 | — |
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| Unresolved product id: 6Server-6.6.AUS:kernel-debuginfo-common-x86_64-0:2.6.32-504.81.3.el6.x86_64 | — |
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| Unresolved product id: 6Server-6.6.AUS:kernel-headers-0:2.6.32-504.81.3.el6.x86_64 | — |
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| Unresolved product id: 6Server-6.6.AUS:python-perf-0:2.6.32-504.81.3.el6.x86_64 | — |
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| Unresolved product id: 6Server-6.6.AUS:python-perf-debuginfo-0:2.6.32-504.81.3.el6.x86_64 | — |
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| Unresolved product id: 6Server-optional-6.6.AUS:kernel-0:2.6.32-504.81.3.el6.src | — |
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| Unresolved product id: 6Server-optional-6.6.AUS:python-perf-debuginfo-0:2.6.32-504.81.3.el6.x86_64 | — |
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"text": "A flaw was found in the way Intel CPUs handle inconsistency between, virtual to physical memory address translations in CPU\u0027s local cache and system software\u0027s Paging structure entries. A privileged guest user may use this flaw to induce a hardware Machine Check Error on the host processor, resulting in a severe DoS scenario by halting the processor.\r\n\r\nSystem software like OS OR Virtual Machine Monitor (VMM) use virtual memory system for storing program instructions and data in memory. Virtual Memory system uses Paging structures like Page Tables and Page Directories to manage system memory. The processor\u0027s Memory Management Unit (MMU) uses Paging structure entries to translate program\u0027s virtual memory addresses to physical memory addresses. The processor stores these address translations into its local cache buffer called - Translation Lookaside Buffer (TLB). TLB has two parts, one for instructions and other for data addresses.\r\n\r\nSystem software can modify its Paging structure entries to change address mappings OR certain attributes like page size etc. Upon such Paging structure alterations in memory, system software must invalidate the corresponding address translations in the processor\u0027s TLB cache. But before this TLB invalidation takes place, a privileged guest user may trigger an instruction fetch operation, which could use an already cached, but now invalid, virtual to physical address translation from Instruction TLB (ITLB). Thus accessing an invalid physical memory address and resulting in halting the processor due to the Machine Check Error (MCE) on Page Size Change.",
"title": "Vulnerability description"
},
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"text": "hw: Machine Check Error on Page Size Change (IFU)",
"title": "Vulnerability summary"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
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"userInteraction": "NONE",
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"title": "hw: Machine Check Error on Page Size Change (IFU)"
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],
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"name": "Observable Discrepancy"
},
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"ids": [
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"text": "1753062"
}
],
"notes": [
{
"category": "description",
"text": "A flaw was found in the way Intel CPUs handle speculative execution of instructions when the TSX Asynchronous Abort (TAA) error occurs. A local authenticated attacker with the ability to monitor execution times could infer the TSX memory state by comparing abort execution times. This could allow information disclosure via this observed side-channel for any TSX transaction being executed while an attacker is able to observe abort timing.\r\n\r\nIntel\u0027s Transactional Synchronisation Extensions (TSX) are set of instructions which enable transactional memory support to improve performance of the multi-threaded applications, in the lock-protected critical sections. The CPU executes instructions in the critical-sections as transactions, while ensuring their atomic state. When such transaction execution is unsuccessful, the processor cannot ensure atomic updates to the transaction memory, so the processor rolls back or aborts such transaction execution.\r\n\r\nWhile TSX Asynchronous Abort (TAA) is pending, CPU may continue to read data from architectural buffers and pass it to the dependent speculative operations. This may cause information leakage via speculative side-channel means, which is quite similar to the Microarchitectural Data Sampling (MDS) issue.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "hw: TSX Transaction Asynchronous Abort (TAA)",
"title": "Vulnerability summary"
},
{
"category": "other",
"text": "libvirt and qemu-kvm on Red Hat Enterprise Linux 6 are not affected by this vulnerability as they do not support MSR-based CPU features.",
"title": "Statement"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
],
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"url": "https://access.redhat.com/security/cve/CVE-2019-11135"
},
{
"category": "external",
"summary": "RHBZ#1753062",
"url": "https://bugzilla.redhat.com/show_bug.cgi?id=1753062"
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{
"category": "external",
"summary": "https://www.cve.org/CVERecord?id=CVE-2019-11135",
"url": "https://www.cve.org/CVERecord?id=CVE-2019-11135"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2019-11135",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2019-11135"
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{
"category": "external",
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"summary": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00270.html",
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"category": "vendor_fix",
"date": "2019-11-12T21:11:25+00:00",
"details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/11258\n\nThe system must be rebooted for this update to take effect.",
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{
"cvss_v3": {
"attackComplexity": "LOW",
"attackVector": "LOCAL",
"availabilityImpact": "NONE",
"baseScore": 6.5,
"baseSeverity": "MEDIUM",
"confidentialityImpact": "HIGH",
"integrityImpact": "NONE",
"privilegesRequired": "LOW",
"scope": "CHANGED",
"userInteraction": "NONE",
"vectorString": "CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:N/A:N",
"version": "3.0"
},
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"threats": [
{
"category": "impact",
"details": "Moderate"
}
],
"title": "hw: TSX Transaction Asynchronous Abort (TAA)"
}
]
}
RHSA-2019_3843
Vulnerability from csaf_redhat - Published: 2019-11-12 21:12 - Updated: 2024-11-15 03:17A flaw was found in the way Intel CPUs handle inconsistency between, virtual to physical memory address translations in CPU's local cache and system software's Paging structure entries. A privileged guest user may use this flaw to induce a hardware Machine Check Error on the host processor, resulting in a severe DoS scenario by halting the processor. System software like OS OR Virtual Machine Monitor (VMM) use virtual memory system for storing program instructions and data in memory. Virtual Memory system uses Paging structures like Page Tables and Page Directories to manage system memory. The processor's Memory Management Unit (MMU) uses Paging structure entries to translate program's virtual memory addresses to physical memory addresses. The processor stores these address translations into its local cache buffer called - Translation Lookaside Buffer (TLB). TLB has two parts, one for instructions and other for data addresses. System software can modify its Paging structure entries to change address mappings OR certain attributes like page size etc. Upon such Paging structure alterations in memory, system software must invalidate the corresponding address translations in the processor's TLB cache. But before this TLB invalidation takes place, a privileged guest user may trigger an instruction fetch operation, which could use an already cached, but now invalid, virtual to physical address translation from Instruction TLB (ITLB). Thus accessing an invalid physical memory address and resulting in halting the processor due to the Machine Check Error (MCE) on Page Size Change.
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A flaw was found in the way Intel CPUs handle speculative execution of instructions when the TSX Asynchronous Abort (TAA) error occurs. A local authenticated attacker with the ability to monitor execution times could infer the TSX memory state by comparing abort execution times. This could allow information disclosure via this observed side-channel for any TSX transaction being executed while an attacker is able to observe abort timing. Intel's Transactional Synchronisation Extensions (TSX) are set of instructions which enable transactional memory support to improve performance of the multi-threaded applications, in the lock-protected critical sections. The CPU executes instructions in the critical-sections as transactions, while ensuring their atomic state. When such transaction execution is unsuccessful, the processor cannot ensure atomic updates to the transaction memory, so the processor rolls back or aborts such transaction execution. While TSX Asynchronous Abort (TAA) is pending, CPU may continue to read data from architectural buffers and pass it to the dependent speculative operations. This may cause information leakage via speculative side-channel means, which is quite similar to the Microarchitectural Data Sampling (MDS) issue.
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{
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"text": "Important"
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"category": "csaf_security_advisory",
"csaf_version": "2.0",
"distribution": {
"text": "Copyright \u00a9 Red Hat, Inc. All rights reserved.",
"tlp": {
"label": "WHITE",
"url": "https://www.first.org/tlp/"
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},
"lang": "en",
"notes": [
{
"category": "summary",
"text": "An update for kernel is now available for Red Hat Enterprise Linux 6.5 Advanced Update Support.\n\nRed Hat Product Security has rated this update as having a security impact of Important. A Common Vulnerability Scoring System (CVSS) base score, which gives a detailed severity rating, is available for each vulnerability from the CVE link(s) in the References section.",
"title": "Topic"
},
{
"category": "general",
"text": "The kernel packages contain the Linux kernel, the core of any Linux operating system.\n\nSecurity Fix(es):\n\n* hw: Machine Check Error on Page Size Change (IFU) (CVE-2018-12207)\n\n* hw: TSX Transaction Asynchronous Abort (TAA) (CVE-2019-11135)\n\nFor more details about the security issue(s), including the impact, a CVSS score, acknowledgments, and other related information, refer to the CVE page(s) listed in the References section.",
"title": "Details"
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{
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"text": "This content is licensed under the Creative Commons Attribution 4.0 International License (https://creativecommons.org/licenses/by/4.0/). If you distribute this content, or a modified version of it, you must provide attribution to Red Hat Inc. and provide a link to the original.",
"title": "Terms of Use"
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}
],
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"text": "A flaw was found in the way Intel CPUs handle inconsistency between, virtual to physical memory address translations in CPU\u0027s local cache and system software\u0027s Paging structure entries. A privileged guest user may use this flaw to induce a hardware Machine Check Error on the host processor, resulting in a severe DoS scenario by halting the processor.\r\n\r\nSystem software like OS OR Virtual Machine Monitor (VMM) use virtual memory system for storing program instructions and data in memory. Virtual Memory system uses Paging structures like Page Tables and Page Directories to manage system memory. The processor\u0027s Memory Management Unit (MMU) uses Paging structure entries to translate program\u0027s virtual memory addresses to physical memory addresses. The processor stores these address translations into its local cache buffer called - Translation Lookaside Buffer (TLB). TLB has two parts, one for instructions and other for data addresses.\r\n\r\nSystem software can modify its Paging structure entries to change address mappings OR certain attributes like page size etc. Upon such Paging structure alterations in memory, system software must invalidate the corresponding address translations in the processor\u0027s TLB cache. But before this TLB invalidation takes place, a privileged guest user may trigger an instruction fetch operation, which could use an already cached, but now invalid, virtual to physical address translation from Instruction TLB (ITLB). Thus accessing an invalid physical memory address and resulting in halting the processor due to the Machine Check Error (MCE) on Page Size Change.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "hw: Machine Check Error on Page Size Change (IFU)",
"title": "Vulnerability summary"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
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},
{
"acknowledgments": [
{
"names": [
"Intel"
]
}
],
"cve": "CVE-2019-11135",
"cwe": {
"id": "CWE-203",
"name": "Observable Discrepancy"
},
"discovery_date": "2019-09-18T00:00:00+00:00",
"ids": [
{
"system_name": "Red Hat Bugzilla ID",
"text": "1753062"
}
],
"notes": [
{
"category": "description",
"text": "A flaw was found in the way Intel CPUs handle speculative execution of instructions when the TSX Asynchronous Abort (TAA) error occurs. A local authenticated attacker with the ability to monitor execution times could infer the TSX memory state by comparing abort execution times. This could allow information disclosure via this observed side-channel for any TSX transaction being executed while an attacker is able to observe abort timing.\r\n\r\nIntel\u0027s Transactional Synchronisation Extensions (TSX) are set of instructions which enable transactional memory support to improve performance of the multi-threaded applications, in the lock-protected critical sections. The CPU executes instructions in the critical-sections as transactions, while ensuring their atomic state. When such transaction execution is unsuccessful, the processor cannot ensure atomic updates to the transaction memory, so the processor rolls back or aborts such transaction execution.\r\n\r\nWhile TSX Asynchronous Abort (TAA) is pending, CPU may continue to read data from architectural buffers and pass it to the dependent speculative operations. This may cause information leakage via speculative side-channel means, which is quite similar to the Microarchitectural Data Sampling (MDS) issue.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "hw: TSX Transaction Asynchronous Abort (TAA)",
"title": "Vulnerability summary"
},
{
"category": "other",
"text": "libvirt and qemu-kvm on Red Hat Enterprise Linux 6 are not affected by this vulnerability as they do not support MSR-based CPU features.",
"title": "Statement"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
],
"product_status": {
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},
"references": [
{
"category": "self",
"summary": "Canonical URL",
"url": "https://access.redhat.com/security/cve/CVE-2019-11135"
},
{
"category": "external",
"summary": "RHBZ#1753062",
"url": "https://bugzilla.redhat.com/show_bug.cgi?id=1753062"
},
{
"category": "external",
"summary": "https://www.cve.org/CVERecord?id=CVE-2019-11135",
"url": "https://www.cve.org/CVERecord?id=CVE-2019-11135"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2019-11135",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2019-11135"
},
{
"category": "external",
"summary": "https://access.redhat.com/solutions/tsx-asynchronousabort",
"url": "https://access.redhat.com/solutions/tsx-asynchronousabort"
},
{
"category": "external",
"summary": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00270.html",
"url": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00270.html"
}
],
"release_date": "2019-11-12T18:00:00+00:00",
"remediations": [
{
"category": "vendor_fix",
"date": "2019-11-12T21:12:23+00:00",
"details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/11258\n\nThe system must be rebooted for this update to take effect.",
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"restart_required": {
"category": "machine"
},
"url": "https://access.redhat.com/errata/RHSA-2019:3843"
},
{
"category": "workaround",
"details": "For mitigation related information, please refer to the Red Hat Knowledgebase article: https://access.redhat.com/solutions/tsx-asynchronousabort",
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"scores": [
{
"cvss_v3": {
"attackComplexity": "LOW",
"attackVector": "LOCAL",
"availabilityImpact": "NONE",
"baseScore": 6.5,
"baseSeverity": "MEDIUM",
"confidentialityImpact": "HIGH",
"integrityImpact": "NONE",
"privilegesRequired": "LOW",
"scope": "CHANGED",
"userInteraction": "NONE",
"vectorString": "CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:N/A:N",
"version": "3.0"
},
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],
"threats": [
{
"category": "impact",
"details": "Moderate"
}
],
"title": "hw: TSX Transaction Asynchronous Abort (TAA)"
}
]
}
RHSA-2019_3844
Vulnerability from csaf_redhat - Published: 2019-11-12 21:08 - Updated: 2024-11-15 03:17A flaw was found in the way Intel CPUs handle inconsistency between, virtual to physical memory address translations in CPU's local cache and system software's Paging structure entries. A privileged guest user may use this flaw to induce a hardware Machine Check Error on the host processor, resulting in a severe DoS scenario by halting the processor. System software like OS OR Virtual Machine Monitor (VMM) use virtual memory system for storing program instructions and data in memory. Virtual Memory system uses Paging structures like Page Tables and Page Directories to manage system memory. The processor's Memory Management Unit (MMU) uses Paging structure entries to translate program's virtual memory addresses to physical memory addresses. The processor stores these address translations into its local cache buffer called - Translation Lookaside Buffer (TLB). TLB has two parts, one for instructions and other for data addresses. System software can modify its Paging structure entries to change address mappings OR certain attributes like page size etc. Upon such Paging structure alterations in memory, system software must invalidate the corresponding address translations in the processor's TLB cache. But before this TLB invalidation takes place, a privileged guest user may trigger an instruction fetch operation, which could use an already cached, but now invalid, virtual to physical address translation from Instruction TLB (ITLB). Thus accessing an invalid physical memory address and resulting in halting the processor due to the Machine Check Error (MCE) on Page Size Change.
| Product | Identifier | Version | Remediation |
|---|---|---|---|
| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-1:3.10.0-693.60.2.rt56.655.el6rt.src | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-debug-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-debug-debuginfo-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-debug-devel-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-debuginfo-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-debuginfo-common-x86_64-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-devel-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-doc-1:3.10.0-693.60.2.rt56.655.el6rt.noarch | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-firmware-1:3.10.0-693.60.2.rt56.655.el6rt.noarch | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-trace-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-trace-debuginfo-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-trace-devel-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-vanilla-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-vanilla-debuginfo-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-vanilla-devel-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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A flaw was found in Intel graphics hardware (GPU) where a local attacker with the ability to issue an ioctl could trigger a hardware level crash if MMIO registers were read while the graphics card was in a low-power state. This creates a denial of service situation and the GPU and connected displays will remain unusable until a reboot occurs.
| Product | Identifier | Version | Remediation |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-1:3.10.0-693.60.2.rt56.655.el6rt.src | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-debug-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-debug-debuginfo-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-debug-devel-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-debuginfo-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-debuginfo-common-x86_64-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-devel-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-doc-1:3.10.0-693.60.2.rt56.655.el6rt.noarch | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-firmware-1:3.10.0-693.60.2.rt56.655.el6rt.noarch | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-trace-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-trace-debuginfo-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-trace-devel-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-vanilla-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-vanilla-debuginfo-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-vanilla-devel-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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A flaw was found in the way Intel CPUs handle speculative execution of instructions when the TSX Asynchronous Abort (TAA) error occurs. A local authenticated attacker with the ability to monitor execution times could infer the TSX memory state by comparing abort execution times. This could allow information disclosure via this observed side-channel for any TSX transaction being executed while an attacker is able to observe abort timing. Intel's Transactional Synchronisation Extensions (TSX) are set of instructions which enable transactional memory support to improve performance of the multi-threaded applications, in the lock-protected critical sections. The CPU executes instructions in the critical-sections as transactions, while ensuring their atomic state. When such transaction execution is unsuccessful, the processor cannot ensure atomic updates to the transaction memory, so the processor rolls back or aborts such transaction execution. While TSX Asynchronous Abort (TAA) is pending, CPU may continue to read data from architectural buffers and pass it to the dependent speculative operations. This may cause information leakage via speculative side-channel means, which is quite similar to the Microarchitectural Data Sampling (MDS) issue.
| Product | Identifier | Version | Remediation |
|---|---|---|---|
| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-1:3.10.0-693.60.2.rt56.655.el6rt.src | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-debug-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-debug-debuginfo-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-debug-devel-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-debuginfo-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-debuginfo-common-x86_64-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-devel-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-doc-1:3.10.0-693.60.2.rt56.655.el6rt.noarch | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-firmware-1:3.10.0-693.60.2.rt56.655.el6rt.noarch | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-trace-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-trace-debuginfo-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-trace-devel-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-vanilla-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-vanilla-debuginfo-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-vanilla-devel-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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"text": "hw: Machine Check Error on Page Size Change (IFU)",
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"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
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"title": "hw: Machine Check Error on Page Size Change (IFU)"
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{
"category": "description",
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"title": "Vulnerability description"
},
{
"category": "summary",
"text": "hw: Intel GPU Denial Of Service while accessing MMIO in lower power state",
"title": "Vulnerability summary"
},
{
"category": "other",
"text": "Intel plans to release BIOS firmware to correct this issue. Red Hat\u0027s kernel update should mitigate this vulnerability. Some older hardware will not have BIOS firmware update and will rely on operating system level protection to prevent access while the device is in low-power states. For more information see https://access.redhat.com/solutions/i915-graphics",
"title": "Statement"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
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"integrityImpact": "NONE",
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"scope": "CHANGED",
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"version": "3.0"
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"title": "hw: Intel GPU Denial Of Service while accessing MMIO in lower power state"
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{
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],
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"ids": [
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"title": "Vulnerability description"
},
{
"category": "summary",
"text": "hw: TSX Transaction Asynchronous Abort (TAA)",
"title": "Vulnerability summary"
},
{
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"text": "libvirt and qemu-kvm on Red Hat Enterprise Linux 6 are not affected by this vulnerability as they do not support MSR-based CPU features.",
"title": "Statement"
},
{
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"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
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{
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"baseScore": 6.5,
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"confidentialityImpact": "HIGH",
"integrityImpact": "NONE",
"privilegesRequired": "LOW",
"scope": "CHANGED",
"userInteraction": "NONE",
"vectorString": "CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:N/A:N",
"version": "3.0"
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}
RHSA-2019_3860
Vulnerability from csaf_redhat - Published: 2019-11-12 20:11 - Updated: 2024-11-15 03:17A flaw was found in the way Intel CPUs handle inconsistency between, virtual to physical memory address translations in CPU's local cache and system software's Paging structure entries. A privileged guest user may use this flaw to induce a hardware Machine Check Error on the host processor, resulting in a severe DoS scenario by halting the processor. System software like OS OR Virtual Machine Monitor (VMM) use virtual memory system for storing program instructions and data in memory. Virtual Memory system uses Paging structures like Page Tables and Page Directories to manage system memory. The processor's Memory Management Unit (MMU) uses Paging structure entries to translate program's virtual memory addresses to physical memory addresses. The processor stores these address translations into its local cache buffer called - Translation Lookaside Buffer (TLB). TLB has two parts, one for instructions and other for data addresses. System software can modify its Paging structure entries to change address mappings OR certain attributes like page size etc. Upon such Paging structure alterations in memory, system software must invalidate the corresponding address translations in the processor's TLB cache. But before this TLB invalidation takes place, a privileged guest user may trigger an instruction fetch operation, which could use an already cached, but now invalid, virtual to physical address translation from Instruction TLB (ITLB). Thus accessing an invalid physical memory address and resulting in halting the processor due to the Machine Check Error (MCE) on Page Size Change.
| Product | Identifier | Version | Remediation |
|---|---|---|---|
| Unresolved product id: 7Server-7.6.EUS-RHV-4.2-Hypervisor-eus:redhat-virtualization-host-0:4.2-20191107.0.el7_6.src | — |
Vendor Fix
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| Unresolved product id: 7Server-7.6.EUS-RHV-4.2-Hypervisor-eus:redhat-virtualization-host-image-update-0:4.2-20191107.0.el7_6.noarch | — |
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| Unresolved product id: 7Server-RHEV-4-Hypervisor-7:redhat-virtualization-host-0:4.3.6-20191108.0.el7_7.src | — |
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| Unresolved product id: 7Server-RHEV-4-Hypervisor-7:redhat-virtualization-host-image-update-0:4.3.6-20191108.0.el7_7.noarch | — |
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| Unresolved product id: 7Server-RHEV-4-HypervisorBuild-7:redhat-virtualization-host-0:4.3.6-20191108.0.el7_7.src | — |
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| Unresolved product id: 7Server-RHEV-4-HypervisorBuild-7:redhat-virtualization-host-image-update-0:4.3.6-20191108.0.el7_7.noarch | — |
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| Product | Identifier | Version | Remediation |
|---|---|---|---|
| Unresolved product id: 7Server-7.6.EUS-RHV-4.2-Hypervisor-eus:redhat-release-virtualization-host-0:4.2-16.1.el7.src | — |
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| Unresolved product id: 7Server-7.6.EUS-RHV-4.2-Hypervisor-eus:redhat-release-virtualization-host-0:4.2-16.1.el7.x86_64 | — |
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| Unresolved product id: 7Server-7.6.EUS-RHV-4.2-Hypervisor-eus:redhat-release-virtualization-host-content-0:4.2-16.1.el7.x86_64 | — |
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| Unresolved product id: 7Server-7.6.EUS-RHV-4.2-Hypervisor-eus:redhat-virtualization-host-image-update-placeholder-0:4.2-16.1.el7.noarch | — |
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| Unresolved product id: 7Server-7.6.EUS-RHV-4.2-HypervisorBuild-eus:redhat-release-virtualization-host-0:4.2-16.1.el7.src | — |
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| Unresolved product id: 7Server-7.6.EUS-RHV-4.2-HypervisorBuild-eus:redhat-release-virtualization-host-0:4.2-16.1.el7.x86_64 | — |
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| Unresolved product id: 7Server-7.6.EUS-RHV-4.2-HypervisorBuild-eus:redhat-release-virtualization-host-content-0:4.2-16.1.el7.x86_64 | — |
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| Unresolved product id: 7Server-7.6.EUS-RHV-4.2-HypervisorBuild-eus:redhat-virtualization-host-image-update-placeholder-0:4.2-16.1.el7.noarch | — |
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| Unresolved product id: 7Server-RHEV-4-HypervisorBuild-7:redhat-release-virtualization-host-0:4.3.6-5.el7ev.src | — |
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| Unresolved product id: 7Server-RHEV-4-HypervisorBuild-7:redhat-release-virtualization-host-0:4.3.6-5.el7ev.x86_64 | — |
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| Unresolved product id: 7Server-RHEV-4-HypervisorBuild-7:redhat-virtualization-host-image-update-placeholder-0:4.3.6-5.el7ev.noarch | — |
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A flaw was found in the way Intel CPUs handle speculative execution of instructions when the TSX Asynchronous Abort (TAA) error occurs. A local authenticated attacker with the ability to monitor execution times could infer the TSX memory state by comparing abort execution times. This could allow information disclosure via this observed side-channel for any TSX transaction being executed while an attacker is able to observe abort timing. Intel's Transactional Synchronisation Extensions (TSX) are set of instructions which enable transactional memory support to improve performance of the multi-threaded applications, in the lock-protected critical sections. The CPU executes instructions in the critical-sections as transactions, while ensuring their atomic state. When such transaction execution is unsuccessful, the processor cannot ensure atomic updates to the transaction memory, so the processor rolls back or aborts such transaction execution. While TSX Asynchronous Abort (TAA) is pending, CPU may continue to read data from architectural buffers and pass it to the dependent speculative operations. This may cause information leakage via speculative side-channel means, which is quite similar to the Microarchitectural Data Sampling (MDS) issue.
| Product | Identifier | Version | Remediation |
|---|---|---|---|
| Unresolved product id: 7Server-7.6.EUS-RHV-4.2-Hypervisor-eus:redhat-virtualization-host-0:4.2-20191107.0.el7_6.src | — |
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| Unresolved product id: 7Server-7.6.EUS-RHV-4.2-Hypervisor-eus:redhat-virtualization-host-image-update-0:4.2-20191107.0.el7_6.noarch | — |
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| Unresolved product id: 7Server-RHEV-4-Hypervisor-7:redhat-virtualization-host-0:4.3.6-20191108.0.el7_7.src | — |
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| Unresolved product id: 7Server-RHEV-4-Hypervisor-7:redhat-virtualization-host-image-update-0:4.3.6-20191108.0.el7_7.noarch | — |
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| Unresolved product id: 7Server-RHEV-4-HypervisorBuild-7:redhat-virtualization-host-0:4.3.6-20191108.0.el7_7.src | — |
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| Unresolved product id: 7Server-RHEV-4-HypervisorBuild-7:redhat-virtualization-host-image-update-0:4.3.6-20191108.0.el7_7.noarch | — |
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| Product | Identifier | Version | Remediation |
|---|---|---|---|
| Unresolved product id: 7Server-7.6.EUS-RHV-4.2-Hypervisor-eus:redhat-release-virtualization-host-0:4.2-16.1.el7.src | — |
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| Unresolved product id: 7Server-7.6.EUS-RHV-4.2-Hypervisor-eus:redhat-release-virtualization-host-0:4.2-16.1.el7.x86_64 | — |
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| Unresolved product id: 7Server-7.6.EUS-RHV-4.2-Hypervisor-eus:redhat-release-virtualization-host-content-0:4.2-16.1.el7.x86_64 | — |
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| Unresolved product id: 7Server-7.6.EUS-RHV-4.2-Hypervisor-eus:redhat-virtualization-host-image-update-placeholder-0:4.2-16.1.el7.noarch | — |
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| Unresolved product id: 7Server-7.6.EUS-RHV-4.2-HypervisorBuild-eus:redhat-release-virtualization-host-0:4.2-16.1.el7.src | — |
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| Unresolved product id: 7Server-7.6.EUS-RHV-4.2-HypervisorBuild-eus:redhat-release-virtualization-host-0:4.2-16.1.el7.x86_64 | — |
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| Unresolved product id: 7Server-7.6.EUS-RHV-4.2-HypervisorBuild-eus:redhat-release-virtualization-host-content-0:4.2-16.1.el7.x86_64 | — |
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| Unresolved product id: 7Server-7.6.EUS-RHV-4.2-HypervisorBuild-eus:redhat-virtualization-host-image-update-placeholder-0:4.2-16.1.el7.noarch | — |
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| Unresolved product id: 7Server-RHEV-4-HypervisorBuild-7:redhat-release-virtualization-host-0:4.3.6-5.el7ev.src | — |
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| Unresolved product id: 7Server-RHEV-4-HypervisorBuild-7:redhat-release-virtualization-host-0:4.3.6-5.el7ev.x86_64 | — |
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| Unresolved product id: 7Server-RHEV-4-HypervisorBuild-7:redhat-virtualization-host-image-update-placeholder-0:4.3.6-5.el7ev.noarch | — |
Workaround
|
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"text": "hw: Machine Check Error on Page Size Change (IFU)",
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"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
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"title": "hw: Machine Check Error on Page Size Change (IFU)"
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"text": "A flaw was found in the way Intel CPUs handle speculative execution of instructions when the TSX Asynchronous Abort (TAA) error occurs. A local authenticated attacker with the ability to monitor execution times could infer the TSX memory state by comparing abort execution times. This could allow information disclosure via this observed side-channel for any TSX transaction being executed while an attacker is able to observe abort timing.\r\n\r\nIntel\u0027s Transactional Synchronisation Extensions (TSX) are set of instructions which enable transactional memory support to improve performance of the multi-threaded applications, in the lock-protected critical sections. The CPU executes instructions in the critical-sections as transactions, while ensuring their atomic state. When such transaction execution is unsuccessful, the processor cannot ensure atomic updates to the transaction memory, so the processor rolls back or aborts such transaction execution.\r\n\r\nWhile TSX Asynchronous Abort (TAA) is pending, CPU may continue to read data from architectural buffers and pass it to the dependent speculative operations. This may cause information leakage via speculative side-channel means, which is quite similar to the Microarchitectural Data Sampling (MDS) issue.",
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"release_date": "2019-11-12T18:00:00+00:00",
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RHSA-2019_3916
Vulnerability from csaf_redhat - Published: 2019-11-19 15:56 - Updated: 2024-11-15 04:12A flaw was found in the way Intel CPUs handle inconsistency between, virtual to physical memory address translations in CPU's local cache and system software's Paging structure entries. A privileged guest user may use this flaw to induce a hardware Machine Check Error on the host processor, resulting in a severe DoS scenario by halting the processor. System software like OS OR Virtual Machine Monitor (VMM) use virtual memory system for storing program instructions and data in memory. Virtual Memory system uses Paging structures like Page Tables and Page Directories to manage system memory. The processor's Memory Management Unit (MMU) uses Paging structure entries to translate program's virtual memory addresses to physical memory addresses. The processor stores these address translations into its local cache buffer called - Translation Lookaside Buffer (TLB). TLB has two parts, one for instructions and other for data addresses. System software can modify its Paging structure entries to change address mappings OR certain attributes like page size etc. Upon such Paging structure alterations in memory, system software must invalidate the corresponding address translations in the processor's TLB cache. But before this TLB invalidation takes place, a privileged guest user may trigger an instruction fetch operation, which could use an already cached, but now invalid, virtual to physical address translation from Instruction TLB (ITLB). Thus accessing an invalid physical memory address and resulting in halting the processor due to the Machine Check Error (MCE) on Page Size Change.
| Product | Identifier | Version | Remediation |
|---|---|---|---|
|
Red Hat OpenShift Container Platform 4
Red Hat / Red Hat OpenShift Enterprise
|
cpe:/a:redhat:openshift:4.2
|
— |
Vendor Fix
fix
Workaround
|
A flaw was found in the way sudo implemented running commands with arbitrary user ID. If a sudoers entry is written to allow the attacker to run a command as any user except root, this flaw can be used by the attacker to bypass that restriction.
| Product | Identifier | Version | Remediation |
|---|---|---|---|
|
Red Hat OpenShift Container Platform 4
Red Hat / Red Hat OpenShift Enterprise
|
cpe:/a:redhat:openshift:4.2
|
— |
Vendor Fix
fix
Workaround
|
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"text": "Red Hat OpenShift Container Platform is Red Hat\u0027s cloud computing Kubernetes application platform solution designed for on-premise or private cloud deployments.\n\nThis is a text-only advisory for the machine-os-content container image, which includes RPM packages for Red Hat Enterprise Linux CoreOS.\n\nSecurity Fix(es):\n\n* A flaw was found in the way Intel CPUs handled inconsistency between virtual to physical memory address translations in the CPU\u0027s local cache and the system software\u0027s Paging structure entries. A privileged guest user can exploit this flaw to induce a hardware Machine Check Error (MCE) on the host processor, resulting in a severe DoS scenario by halting the processor. System software like the OS OR Virtual Machine Monitor (VMM) use the virtual memory system for storing program instructions and data in memory. The virtual memory system uses Paging structures like Page Tables and Page Directories to manage system memory. The processor\u0027s Memory Management Unit (MMU) uses Paging structure entries to translate a program\u0027s virtual memory addresses to physical memory addresses. The processor stores these address translations into its local cache buffer, called the Translation Lookaside Buffer (TLB). TLB has two parts, one for instructions and the other for data addresses. System software can modify its Paging structure entries to change address mappings or certain attributes like page size, etc. Upon such Paging structure alterations in memory, system software must invalidate the corresponding address translations in the processor\u0027s TLB cache. Before this TLB invalidation takes place, however, a privileged guest user could trigger an instruction fetch operation, which could use an already cached, but now invalid, virtual to physical address translation from Instruction TLB (ITLB). This would access an invalid physical memory address, resulting in halting the processor due to the MCE on Page Size Change. (CVE-2018-12207)\n\n* A flaw was found in the way sudo implemented running commands with an arbitrary user ID. If a sudoers entry is written to allow users to run a command as any user except root, this flaw can be used by an attacker to bypass that restriction. (CVE-2019-14287)\n\nFor more details about the security issue(s), including the impact, a CVSS score, acknowledgments, and other related information, refer to the CVE page(s) listed in the References section.",
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"text": "A flaw was found in the way Intel CPUs handle inconsistency between, virtual to physical memory address translations in CPU\u0027s local cache and system software\u0027s Paging structure entries. A privileged guest user may use this flaw to induce a hardware Machine Check Error on the host processor, resulting in a severe DoS scenario by halting the processor.\r\n\r\nSystem software like OS OR Virtual Machine Monitor (VMM) use virtual memory system for storing program instructions and data in memory. Virtual Memory system uses Paging structures like Page Tables and Page Directories to manage system memory. The processor\u0027s Memory Management Unit (MMU) uses Paging structure entries to translate program\u0027s virtual memory addresses to physical memory addresses. The processor stores these address translations into its local cache buffer called - Translation Lookaside Buffer (TLB). TLB has two parts, one for instructions and other for data addresses.\r\n\r\nSystem software can modify its Paging structure entries to change address mappings OR certain attributes like page size etc. Upon such Paging structure alterations in memory, system software must invalidate the corresponding address translations in the processor\u0027s TLB cache. But before this TLB invalidation takes place, a privileged guest user may trigger an instruction fetch operation, which could use an already cached, but now invalid, virtual to physical address translation from Instruction TLB (ITLB). Thus accessing an invalid physical memory address and resulting in halting the processor due to the Machine Check Error (MCE) on Page Size Change.",
"title": "Vulnerability description"
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},
{
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"url": "https://nvd.nist.gov/vuln/detail/CVE-2018-12207"
},
{
"category": "external",
"summary": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00210.html",
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"date": "2019-11-19T15:56:26+00:00",
"details": "See the following documentation, which will be updated shortly for release 4.2.5, for important instructions on how to upgrade your cluster and fully apply this asynchronous errata update:\n\nhttps://docs.openshift.com/container-platform/4.2/release_notes/ocp-4-2-release-notes.html",
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"category": "none"
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},
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"baseScore": 6.5,
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"confidentialityImpact": "NONE",
"integrityImpact": "NONE",
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"scope": "CHANGED",
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"title": "hw: Machine Check Error on Page Size Change (IFU)"
},
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"title": "Vulnerability description"
},
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},
{
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RHSA-2019_3936
Vulnerability from csaf_redhat - Published: 2019-11-22 08:52 - Updated: 2024-11-15 03:18A flaw was found in the way Intel CPUs handle inconsistency between, virtual to physical memory address translations in CPU's local cache and system software's Paging structure entries. A privileged guest user may use this flaw to induce a hardware Machine Check Error on the host processor, resulting in a severe DoS scenario by halting the processor. System software like OS OR Virtual Machine Monitor (VMM) use virtual memory system for storing program instructions and data in memory. Virtual Memory system uses Paging structures like Page Tables and Page Directories to manage system memory. The processor's Memory Management Unit (MMU) uses Paging structure entries to translate program's virtual memory addresses to physical memory addresses. The processor stores these address translations into its local cache buffer called - Translation Lookaside Buffer (TLB). TLB has two parts, one for instructions and other for data addresses. System software can modify its Paging structure entries to change address mappings OR certain attributes like page size etc. Upon such Paging structure alterations in memory, system software must invalidate the corresponding address translations in the processor's TLB cache. But before this TLB invalidation takes place, a privileged guest user may trigger an instruction fetch operation, which could use an already cached, but now invalid, virtual to physical address translation from Instruction TLB (ITLB). Thus accessing an invalid physical memory address and resulting in halting the processor due to the Machine Check Error (MCE) on Page Size Change.
| Product | Identifier | Version | Remediation |
|---|---|---|---|
| Unresolved product id: BaseOS-8.1.0.Z.MAIN.EUS:kpatch-patch-4_18_0-147-0:1-3.el8_1.src | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: BaseOS-8.1.0.Z.MAIN.EUS:kpatch-patch-4_18_0-147-0:1-3.el8_1.x86_64 | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: BaseOS-8.1.0.Z.MAIN.EUS:kpatch-patch-4_18_0-147-debuginfo-0:1-3.el8_1.x86_64 | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: BaseOS-8.1.0.Z.MAIN.EUS:kpatch-patch-4_18_0-147-debugsource-0:1-3.el8_1.x86_64 | — |
Vendor Fix
fix
Workaround
|
A flaw was found in the way Intel CPUs handle speculative execution of instructions when the TSX Asynchronous Abort (TAA) error occurs. A local authenticated attacker with the ability to monitor execution times could infer the TSX memory state by comparing abort execution times. This could allow information disclosure via this observed side-channel for any TSX transaction being executed while an attacker is able to observe abort timing. Intel's Transactional Synchronisation Extensions (TSX) are set of instructions which enable transactional memory support to improve performance of the multi-threaded applications, in the lock-protected critical sections. The CPU executes instructions in the critical-sections as transactions, while ensuring their atomic state. When such transaction execution is unsuccessful, the processor cannot ensure atomic updates to the transaction memory, so the processor rolls back or aborts such transaction execution. While TSX Asynchronous Abort (TAA) is pending, CPU may continue to read data from architectural buffers and pass it to the dependent speculative operations. This may cause information leakage via speculative side-channel means, which is quite similar to the Microarchitectural Data Sampling (MDS) issue.
| Product | Identifier | Version | Remediation |
|---|---|---|---|
| Unresolved product id: BaseOS-8.1.0.Z.MAIN.EUS:kpatch-patch-4_18_0-147-0:1-3.el8_1.src | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: BaseOS-8.1.0.Z.MAIN.EUS:kpatch-patch-4_18_0-147-0:1-3.el8_1.x86_64 | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: BaseOS-8.1.0.Z.MAIN.EUS:kpatch-patch-4_18_0-147-debuginfo-0:1-3.el8_1.x86_64 | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: BaseOS-8.1.0.Z.MAIN.EUS:kpatch-patch-4_18_0-147-debugsource-0:1-3.el8_1.x86_64 | — |
Vendor Fix
fix
Workaround
|
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"cwe": {
"id": "CWE-226",
"name": "Sensitive Information in Resource Not Removed Before Reuse"
},
"discovery_date": "2018-11-06T00:00:00+00:00",
"ids": [
{
"system_name": "Red Hat Bugzilla ID",
"text": "1646768"
}
],
"notes": [
{
"category": "description",
"text": "A flaw was found in the way Intel CPUs handle inconsistency between, virtual to physical memory address translations in CPU\u0027s local cache and system software\u0027s Paging structure entries. A privileged guest user may use this flaw to induce a hardware Machine Check Error on the host processor, resulting in a severe DoS scenario by halting the processor.\r\n\r\nSystem software like OS OR Virtual Machine Monitor (VMM) use virtual memory system for storing program instructions and data in memory. Virtual Memory system uses Paging structures like Page Tables and Page Directories to manage system memory. The processor\u0027s Memory Management Unit (MMU) uses Paging structure entries to translate program\u0027s virtual memory addresses to physical memory addresses. The processor stores these address translations into its local cache buffer called - Translation Lookaside Buffer (TLB). TLB has two parts, one for instructions and other for data addresses.\r\n\r\nSystem software can modify its Paging structure entries to change address mappings OR certain attributes like page size etc. Upon such Paging structure alterations in memory, system software must invalidate the corresponding address translations in the processor\u0027s TLB cache. But before this TLB invalidation takes place, a privileged guest user may trigger an instruction fetch operation, which could use an already cached, but now invalid, virtual to physical address translation from Instruction TLB (ITLB). Thus accessing an invalid physical memory address and resulting in halting the processor due to the Machine Check Error (MCE) on Page Size Change.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "hw: Machine Check Error on Page Size Change (IFU)",
"title": "Vulnerability summary"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
],
"product_status": {
"fixed": [
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]
},
"references": [
{
"category": "self",
"summary": "Canonical URL",
"url": "https://access.redhat.com/security/cve/CVE-2018-12207"
},
{
"category": "external",
"summary": "RHBZ#1646768",
"url": "https://bugzilla.redhat.com/show_bug.cgi?id=1646768"
},
{
"category": "external",
"summary": "RHSB-ifu-page-mce",
"url": "https://access.redhat.com/security/vulnerabilities/ifu-page-mce"
},
{
"category": "external",
"summary": "https://www.cve.org/CVERecord?id=CVE-2018-12207",
"url": "https://www.cve.org/CVERecord?id=CVE-2018-12207"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2018-12207",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2018-12207"
},
{
"category": "external",
"summary": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00210.html",
"url": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00210.html"
}
],
"release_date": "2019-11-12T18:00:00+00:00",
"remediations": [
{
"category": "vendor_fix",
"date": "2019-11-22T08:52:34+00:00",
"details": "Before applying this update, make sure all previously released errata relevant to your system have been applied.\n\nFor details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/11258",
"product_ids": [
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],
"restart_required": {
"category": "none"
},
"url": "https://access.redhat.com/errata/RHSA-2019:3936"
},
{
"category": "workaround",
"details": "For mitigation related information, please refer to the Red Hat vulnerability article: https://access.redhat.com/security/vulnerabilities/ifu-page-mce .",
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]
}
],
"scores": [
{
"cvss_v3": {
"attackComplexity": "LOW",
"attackVector": "LOCAL",
"availabilityImpact": "HIGH",
"baseScore": 6.5,
"baseSeverity": "MEDIUM",
"confidentialityImpact": "NONE",
"integrityImpact": "NONE",
"privilegesRequired": "LOW",
"scope": "CHANGED",
"userInteraction": "NONE",
"vectorString": "CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:N/I:N/A:H",
"version": "3.0"
},
"products": [
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"BaseOS-8.1.0.Z.MAIN.EUS:kpatch-patch-4_18_0-147-0:1-3.el8_1.x86_64",
"BaseOS-8.1.0.Z.MAIN.EUS:kpatch-patch-4_18_0-147-debuginfo-0:1-3.el8_1.x86_64",
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]
}
],
"threats": [
{
"category": "impact",
"details": "Important"
}
],
"title": "hw: Machine Check Error on Page Size Change (IFU)"
},
{
"acknowledgments": [
{
"names": [
"Intel"
]
}
],
"cve": "CVE-2019-11135",
"cwe": {
"id": "CWE-203",
"name": "Observable Discrepancy"
},
"discovery_date": "2019-09-18T00:00:00+00:00",
"ids": [
{
"system_name": "Red Hat Bugzilla ID",
"text": "1753062"
}
],
"notes": [
{
"category": "description",
"text": "A flaw was found in the way Intel CPUs handle speculative execution of instructions when the TSX Asynchronous Abort (TAA) error occurs. A local authenticated attacker with the ability to monitor execution times could infer the TSX memory state by comparing abort execution times. This could allow information disclosure via this observed side-channel for any TSX transaction being executed while an attacker is able to observe abort timing.\r\n\r\nIntel\u0027s Transactional Synchronisation Extensions (TSX) are set of instructions which enable transactional memory support to improve performance of the multi-threaded applications, in the lock-protected critical sections. The CPU executes instructions in the critical-sections as transactions, while ensuring their atomic state. When such transaction execution is unsuccessful, the processor cannot ensure atomic updates to the transaction memory, so the processor rolls back or aborts such transaction execution.\r\n\r\nWhile TSX Asynchronous Abort (TAA) is pending, CPU may continue to read data from architectural buffers and pass it to the dependent speculative operations. This may cause information leakage via speculative side-channel means, which is quite similar to the Microarchitectural Data Sampling (MDS) issue.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "hw: TSX Transaction Asynchronous Abort (TAA)",
"title": "Vulnerability summary"
},
{
"category": "other",
"text": "libvirt and qemu-kvm on Red Hat Enterprise Linux 6 are not affected by this vulnerability as they do not support MSR-based CPU features.",
"title": "Statement"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
],
"product_status": {
"fixed": [
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]
},
"references": [
{
"category": "self",
"summary": "Canonical URL",
"url": "https://access.redhat.com/security/cve/CVE-2019-11135"
},
{
"category": "external",
"summary": "RHBZ#1753062",
"url": "https://bugzilla.redhat.com/show_bug.cgi?id=1753062"
},
{
"category": "external",
"summary": "https://www.cve.org/CVERecord?id=CVE-2019-11135",
"url": "https://www.cve.org/CVERecord?id=CVE-2019-11135"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2019-11135",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2019-11135"
},
{
"category": "external",
"summary": "https://access.redhat.com/solutions/tsx-asynchronousabort",
"url": "https://access.redhat.com/solutions/tsx-asynchronousabort"
},
{
"category": "external",
"summary": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00270.html",
"url": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00270.html"
}
],
"release_date": "2019-11-12T18:00:00+00:00",
"remediations": [
{
"category": "vendor_fix",
"date": "2019-11-22T08:52:34+00:00",
"details": "Before applying this update, make sure all previously released errata relevant to your system have been applied.\n\nFor details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/11258",
"product_ids": [
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"restart_required": {
"category": "none"
},
"url": "https://access.redhat.com/errata/RHSA-2019:3936"
},
{
"category": "workaround",
"details": "For mitigation related information, please refer to the Red Hat Knowledgebase article: https://access.redhat.com/solutions/tsx-asynchronousabort",
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}
],
"scores": [
{
"cvss_v3": {
"attackComplexity": "LOW",
"attackVector": "LOCAL",
"availabilityImpact": "NONE",
"baseScore": 6.5,
"baseSeverity": "MEDIUM",
"confidentialityImpact": "HIGH",
"integrityImpact": "NONE",
"privilegesRequired": "LOW",
"scope": "CHANGED",
"userInteraction": "NONE",
"vectorString": "CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:N/A:N",
"version": "3.0"
},
"products": [
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]
}
],
"threats": [
{
"category": "impact",
"details": "Moderate"
}
],
"title": "hw: TSX Transaction Asynchronous Abort (TAA)"
}
]
}
Sightings
| Author | Source | Type | Date | Other |
|---|
Nomenclature
- Seen: The vulnerability was mentioned, discussed, or observed by the user.
- Confirmed: The vulnerability has been validated from an analyst's perspective.
- Published Proof of Concept: A public proof of concept is available for this vulnerability.
- Exploited: The vulnerability was observed as exploited by the user who reported the sighting.
- Patched: The vulnerability was observed as successfully patched by the user who reported the sighting.
- Not exploited: The vulnerability was not observed as exploited by the user who reported the sighting.
- Not confirmed: The user expressed doubt about the validity of the vulnerability.
- Not patched: The vulnerability was not observed as successfully patched by the user who reported the sighting.