CVE-2026-53354 (GCVE-0-2026-53354)

Vulnerability from cvelistv5 – Published: 2026-07-01 13:32 – Updated: 2026-08-05 12:35
VLAI
Title
arm64: errata: Mitigate TLBI errata on various Arm CPUs
Summary
In the Linux kernel, the following vulnerability has been resolved: arm64: errata: Mitigate TLBI errata on various Arm CPUs A number of CPUs developed by Arm suffer from errata whereby a broadcast TLBI;DSB sequence may complete before the global observation of writes which are translated by an affected TLB entry. These errata ONLY affect the completion of memory accesses which have been translated by an invalidated TLB entry, and these errata DO NOT affect the actual invalidation of TLB entries. TLB entries are removed correctly. This issue has been assigned CVE ID CVE-2025-10263. To mitigate this issue, Arm recommends that software follows any affected TLBI;DSB sequence with an additional TLBI;DSB, which will ensure that all memory write effects affected by the first TLBI have been globally observed. The additional TLBI can use any operation that is broadcast to affected CPUs, and the additional DSB can use any option that is sufficient to complete the additional TLBI. The ARM64_WORKAROUND_REPEAT_TLBI workaround is sufficient to mitigate the issue. Enable this workaround for affected CPUs, and update the silicon errata documentation accordingly. Note that due to the manner in which Arm develops IP and tracks errata, some CPUs share a common erratum number.
Severity
8.8 (High)
CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:H/A:H
Assigner
References
Impacted products
Vendor Product Version
Linux Linux Affected: 58d0ba578bc3b7c044d4ef570307bcb03862cb66 , < 925058203229403008d77a52b1e63e2ae5f4a3cf (git)
Affected: 58d0ba578bc3b7c044d4ef570307bcb03862cb66 , < 8364384ae82fbffdf8968abaac3455ed854da18d (git)
Affected: 58d0ba578bc3b7c044d4ef570307bcb03862cb66 , < 7c3ad9365079e716b57d2363d3081ee7680cc18e (git)
Affected: 58d0ba578bc3b7c044d4ef570307bcb03862cb66 , < e717a4d08779f1a28d6e0275e75040b12c33c753 (git)
Affected: 58d0ba578bc3b7c044d4ef570307bcb03862cb66 , < 4e7c80742e6dada9f8b9ad63f3a49c03af07ecb8 (git)
Affected: 58d0ba578bc3b7c044d4ef570307bcb03862cb66 , < d4fd4282204044fdedd1e42abbe70a9206f74ec0 (git)
Affected: 58d0ba578bc3b7c044d4ef570307bcb03862cb66 , < 1b47b1e1d8675fdf5f6e11e7fa19c704d8c6f5cd (git)
Affected: 58d0ba578bc3b7c044d4ef570307bcb03862cb66 , < 1268c64e2bcb6e968152990e87bd10c440fcc9c0 (git)
Affected: 58d0ba578bc3b7c044d4ef570307bcb03862cb66 , < cfd391e74134db664feb499d43af286380b10ba8 (git)
Create a notification for this product.
Linux Linux Affected: 3.7
Unaffected: 0 , < 3.7 (semver)
Unaffected: 5.10.259 , ≤ 5.10.* (semver)
Unaffected: 5.15.210 , ≤ 5.15.* (semver)
Unaffected: 6.1.176 , ≤ 6.1.* (semver)
Unaffected: 6.6.143 , ≤ 6.6.* (semver)
Unaffected: 6.12.94 , ≤ 6.12.* (semver)
Unaffected: 6.18.36 , ≤ 6.18.* (semver)
Unaffected: 7.0.13 , ≤ 7.0.* (semver)
Unaffected: 7.1.1 , ≤ 7.1.* (semver)
Unaffected: 7.2-rc1 , ≤ * (original_commit_for_fix)
Create a notification for this product.
Show details on NVD website
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          "value": "In the Linux kernel, the following vulnerability has been resolved:\n\narm64: errata: Mitigate TLBI errata on various Arm CPUs\n\nA number of CPUs developed by Arm suffer from errata whereby a broadcast\nTLBI;DSB sequence may complete before the global observation of writes\nwhich are translated by an affected TLB entry.\n\nThese errata ONLY affect the completion of memory accesses which have\nbeen translated by an invalidated TLB entry, and these errata DO NOT\naffect the actual invalidation of TLB entries. TLB entries are removed\ncorrectly.\n\nThis issue has been assigned CVE ID CVE-2025-10263.\n\nTo mitigate this issue, Arm recommends that software follows any\naffected TLBI;DSB sequence with an additional TLBI;DSB, which will\nensure that all memory write effects affected by the first TLBI have\nbeen globally observed. The additional TLBI can use any operation that\nis broadcast to affected CPUs, and the additional DSB can use any option\nthat is sufficient to complete the additional TLBI.\n\nThe ARM64_WORKAROUND_REPEAT_TLBI workaround is sufficient to mitigate\nthe issue. Enable this workaround for affected CPUs, and update the\nsilicon errata documentation accordingly.\n\nNote that due to the manner in which Arm develops IP and tracks errata,\nsome CPUs share a common erratum number."
        }
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            "baseSeverity": "HIGH",
            "vectorString": "CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:H/A:H",
            "version": "3.1"
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            {
              "lang": "en",
              "value": "AV:L - The vulnerable TLBI completion path is reachable by locally executing code that drives memory permission/unmap activity through syscalls or guest/KVM memory-management activity. It is not directly exposed by network packets.\nAC:L - Although the erratum depends on timing, the attacker can repeatedly arrange concurrent stores and translation invalidations on affected multicore Arm systems. The triggering race is therefore attacker-influenced rather than dependent on a one-off external condition.\nPR:L - A basic unprivileged local user or guest workload can reach the relevant Stage-1/Stage-2 TLBI paths without host administrative privileges. No real root capability in the init namespace is required.\nUI:N - After the attacker has local code execution, exploitation only requires attacker-driven memory operations/syscalls or guest activity. No separate victim action is needed.\nS:C - In a severe reasonable deployment such as Arm KVM/cloud virtualization, bypassing Stage-2 or higher-level translation protections can let guest-controlled writes affect hypervisor/host resources. That crosses a security authority boundary.\nC:H - The primitive can enable privilege escalation to kernel or hypervisor context, making protected memory and secrets accessible. Even though the erratum affects stores, successful control of privileged context supports high confidentiality impact.\nI:H - The core issue permits writes to memory after translation permissions or ownership should have been revoked. This is a high-integrity memory corruption primitive with plausible kernel or hypervisor privilege escalation.\nA:H - Incorrect late writes into protected or reused memory can corrupt kernel/hypervisor state. Failed exploitation or corruption can plausibly cause kernel panic, guest/host crash, or system instability."
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        "shortName": "Linux"
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        },
        {
          "url": "https://git.kernel.org/stable/c/cfd391e74134db664feb499d43af286380b10ba8"
        }
      ],
      "title": "arm64: errata: Mitigate TLBI errata on various Arm CPUs",
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    "assignerShortName": "Linux",
    "cveId": "CVE-2026-53354",
    "datePublished": "2026-07-01T13:32:30.246Z",
    "dateReserved": "2026-06-09T07:44:35.400Z",
    "dateUpdated": "2026-08-05T12:35:03.461Z",
    "state": "PUBLISHED"
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      "cve": "CVE-2026-53354",
      "date": "2026-08-12",
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      "percentile": "0.0238"
    },
    "microsoft_vex": {
      "current_release_date": "2026-07-09T01:44:00.000Z",
      "cve": "CVE-2026-53354",
      "id": "msrc_CVE-2026-53354",
      "initial_release_date": "2026-07-02T00:00:00.000Z",
      "product_status:fixed": "1",
      "product_status:known_affected": "1",
      "source": "Microsoft CSAF VEX",
      "status": "final",
      "title": "arm64: errata: Mitigate TLBI errata on various Arm CPUs",
      "url": "https://msrc.microsoft.com/csaf/vex/2026/msrc_cve-2026-53354.json",
      "version": "3"
    },
    "nvd": "{\"cve\":{\"id\":\"CVE-2026-53354\",\"sourceIdentifier\":\"416baaa9-dc9f-4396-8d5f-8c081fb06d67\",\"published\":\"2026-07-01T14:16:43.627\",\"lastModified\":\"2026-07-22T19:14:41.780\",\"vulnStatus\":\"Analyzed\",\"cveTags\":[],\"descriptions\":[{\"lang\":\"en\",\"value\":\"In the Linux kernel, the following vulnerability has been resolved:\\n\\narm64: errata: Mitigate TLBI errata on various Arm CPUs\\n\\nA number of CPUs developed by Arm suffer from errata whereby a broadcast\\nTLBI;DSB sequence may complete before the global observation of writes\\nwhich are translated by an affected TLB entry.\\n\\nThese errata ONLY affect the completion of memory accesses which have\\nbeen translated by an invalidated TLB entry, and these errata DO NOT\\naffect the actual invalidation of TLB entries. TLB entries are removed\\ncorrectly.\\n\\nThis issue has been assigned CVE ID CVE-2025-10263.\\n\\nTo mitigate this issue, Arm recommends that software follows any\\naffected TLBI;DSB sequence with an additional TLBI;DSB, which will\\nensure that all memory write effects affected by the first TLBI have\\nbeen globally observed. The additional TLBI can use any operation that\\nis broadcast to affected CPUs, and the additional DSB can use any option\\nthat is sufficient to complete the additional TLBI.\\n\\nThe ARM64_WORKAROUND_REPEAT_TLBI workaround is sufficient to mitigate\\nthe issue. Enable this workaround for affected CPUs, and update the\\nsilicon errata documentation accordingly.\\n\\nNote that due to the manner in which Arm develops IP and tracks errata,\\nsome CPUs share a common erratum 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    "redhat_vex": {
      "aggregate_severity": "Moderate",
      "current_release_date": "2026-07-18T08:05:29+00:00",
      "cve": "CVE-2026-53354",
      "id": "CVE-2026-53354",
      "initial_release_date": "2026-07-01T00:00:00+00:00",
      "product_status:known_affected": "232",
      "product_status:known_not_affected": "42",
      "source": "Red Hat CSAF VEX",
      "status": "final",
      "title": "kernel: arm64: errata: Mitigate TLBI errata on various Arm CPUs",
      "url": "https://security.access.redhat.com/data/csaf/v2/vex/2026/cve-2026-53354.json",
      "version": "3"
    },
    "suse_vex": {
      "aggregate_severity": "important",
      "current_release_date": "2026-08-10T16:28:11Z",
      "cve": "CVE-2026-53354",
      "id": "CVE-2026-53354",
      "initial_release_date": "2026-07-03T03:03:43Z",
      "product_status:first_fixed": "223",
      "product_status:known_affected": "26",
      "product_status:known_not_affected": "253",
      "product_status:recommended": "4",
      "source": "SUSE CSAF VEX",
      "status": "interim",
      "title": "SUSE CVE CVE-2026-53354",
      "url": "https://ftp.suse.com/pub/projects/security/csaf-vex/cve-2026-53354.json",
      "version": "6"
    }
  }
}



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Taxonomy of the tags.





Forecast uses a logistic model when the trend is rising, or an exponential decay model when the trend is falling. Fitted via linearized least squares.

Sightings

Author Source Type Date Other

Nomenclature

  • Seen: The vulnerability was mentioned, discussed, or observed by the user.
  • Confirmed: The vulnerability has been validated from an analyst's perspective.
  • Published Proof of Concept: A public proof of concept is available for this vulnerability.
  • Exploited: The vulnerability was observed as exploited by the user who reported the sighting.
  • Patched: The vulnerability was observed as successfully patched by the user who reported the sighting.
  • Not exploited: The vulnerability was not observed as exploited by the user who reported the sighting.
  • Not confirmed: The user expressed doubt about the validity of the vulnerability.
  • Not patched: The vulnerability was not observed as successfully patched by the user who reported the sighting.


Detection rules are retrieved from Rulezet.