CVE-2026-45894 (GCVE-0-2026-45894)

Vulnerability from cvelistv5 – Published: 2026-05-27 12:17 – Updated: 2026-08-05 12:28
VLAI
Title
iommu/vt-d: Clear Present bit before tearing down PASID entry
Summary
In the Linux kernel, the following vulnerability has been resolved: iommu/vt-d: Clear Present bit before tearing down PASID entry The Intel VT-d Scalable Mode PASID table entry consists of 512 bits (64 bytes). When tearing down an entry, the current implementation zeros the entire 64-byte structure immediately using multiple 64-bit writes. Since the IOMMU hardware may fetch these 64 bytes using multiple internal transactions (e.g., four 128-bit bursts), updating or zeroing the entire entry while it is active (P=1) risks a "torn" read. If a hardware fetch occurs simultaneously with the CPU zeroing the entry, the hardware could observe an inconsistent state, leading to unpredictable behavior or spurious faults. Follow the "Guidance to Software for Invalidations" in the VT-d spec (Section 6.5.3.3) by implementing the recommended ownership handshake: 1. Clear only the 'Present' (P) bit of the PASID entry. 2. Use a dma_wmb() to ensure the cleared bit is visible to hardware before proceeding. 3. Execute the required invalidation sequence (PASID cache, IOTLB, and Device-TLB flush) to ensure the hardware has released all cached references. 4. Only after the flushes are complete, zero out the remaining fields of the PASID entry. Also, add a dma_wmb() in pasid_set_present() to ensure that all other fields of the PASID entry are visible to the hardware before the Present bit is set.
Severity
7.8 (High)
CVSS:3.1/AV:L/AC:H/PR:L/UI:N/S:C/C:H/I:H/A:H
Assigner
References
Impacted products
Vendor Product Version
Linux Linux Affected: 0bbeb01a4fafbf8422e5c8882d461d6ac4f71e15 , < a84d30e8d2bacd21782a6481158b7c9c552f4868 (git)
Affected: 0bbeb01a4fafbf8422e5c8882d461d6ac4f71e15 , < 821807c167b7b48a41b95b6607c6b9f97600f7d9 (git)
Affected: 0bbeb01a4fafbf8422e5c8882d461d6ac4f71e15 , < 949d71666e9dd19f21e7b4b53a88cd2c5b902858 (git)
Affected: 0bbeb01a4fafbf8422e5c8882d461d6ac4f71e15 , < 75ed00055c059dedc47b5daaaa2f8a7a019138ff (git)
Create a notification for this product.
Linux Linux Affected: 5.0
Unaffected: 0 , < 5.0 (semver)
Unaffected: 6.12.75 , ≤ 6.12.* (semver)
Unaffected: 6.18.14 , ≤ 6.18.* (semver)
Unaffected: 6.19.4 , ≤ 6.19.* (semver)
Unaffected: 7.0 , ≤ * (original_commit_for_fix)
Create a notification for this product.
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          "value": "In the Linux kernel, the following vulnerability has been resolved:\n\niommu/vt-d: Clear Present bit before tearing down PASID entry\n\nThe Intel VT-d Scalable Mode PASID table entry consists of 512 bits (64\nbytes). When tearing down an entry, the current implementation zeros the\nentire 64-byte structure immediately using multiple 64-bit writes.\n\nSince the IOMMU hardware may fetch these 64 bytes using multiple\ninternal transactions (e.g., four 128-bit bursts), updating or zeroing\nthe entire entry while it is active (P=1) risks a \"torn\" read. If a\nhardware fetch occurs simultaneously with the CPU zeroing the entry, the\nhardware could observe an inconsistent state, leading to unpredictable\nbehavior or spurious faults.\n\nFollow the \"Guidance to Software for Invalidations\" in the VT-d spec\n(Section 6.5.3.3) by implementing the recommended ownership handshake:\n\n1. Clear only the \u0027Present\u0027 (P) bit of the PASID entry.\n2. Use a dma_wmb() to ensure the cleared bit is visible to hardware\n   before proceeding.\n3. Execute the required invalidation sequence (PASID cache, IOTLB, and\n   Device-TLB flush) to ensure the hardware has released all cached\n   references.\n4. Only after the flushes are complete, zero out the remaining fields\n   of the PASID entry.\n\nAlso, add a dma_wmb() in pasid_set_present() to ensure that all other\nfields of the PASID entry are visible to the hardware before the Present\nbit is set."
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              "value": "AV:L - The teardown path is reached only through local interfaces \u2014 IOMMU domain attach/detach, SVA bind/unbind via accelerator char devices, and VFIO/iommufd ioctls \u2014 plus a locally-controlled device\u0027s DMA; there is no remote/network path to this code.\nAC:H - Triggering the torn read requires the IOMMU\u0027s internal multi-burst fetch of the 64-byte entry to interleave with the CPU\u0027s eight 64-bit zeroing writes during the narrow teardown window; this sub-microsecond hardware-internal timing is beyond the attacker\u0027s control and cannot be reliably reproduced.\nPR:L - Reaching the teardown requires local access to manage an IOMMU domain or to bind/unbind a PASID on an SVA-capable accelerator (reachable by an unprivileged user granted device access), not a pre-auth or fully unauthenticated path.\nUI:N - No victim interaction is needed; the attacker drives both the device DMA and the PASID-entry teardown.\nS:C - The IOMMU enforces the DMA isolation boundary; a torn/inconsistent PASID-entry read can cause the IOMMU to mistranslate a device\u0027s DMA, allowing access outside the device\u0027s authorized memory scope \u2014 an IOMMU/DMA boundary crossing.\nC:H - Mistranslation from an inconsistent entry read could let a device (e.g., guest-assigned or SVA-bound) read host physical memory outside its domain, yielding disclosure of memory beyond its authorized scope.\nI:H - The same mistranslation could let a device perform DMA writes to host physical memory outside its assigned domain, corrupting memory across the isolation boundary.\nA:H - The torn read causes \"spurious faults\" and \"unpredictable\" IOMMU behavior, which can produce DMA fault storms or device/translation failures impacting availability."
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    "dateReserved": "2026-05-13T15:03:33.083Z",
    "dateUpdated": "2026-08-05T12:28:39.976Z",
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      "title": "iommu/vt-d: Clear Present bit before tearing down PASID entry",
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      "version": "8"
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If a\\nhardware fetch occurs simultaneously with the CPU zeroing the entry, the\\nhardware could observe an inconsistent state, leading to unpredictable\\nbehavior or spurious faults.\\n\\nFollow the \\\"Guidance to Software for Invalidations\\\" in the VT-d spec\\n(Section 6.5.3.3) by implementing the recommended ownership handshake:\\n\\n1. Clear only the \u0027Present\u0027 (P) bit of the PASID entry.\\n2. Use a dma_wmb() to ensure the cleared bit is visible to hardware\\n   before proceeding.\\n3. Execute the required invalidation sequence (PASID cache, IOTLB, and\\n   Device-TLB flush) to ensure the hardware has released all cached\\n   references.\\n4. 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    "redhat_vex": {
      "aggregate_severity": "Moderate",
      "current_release_date": "2026-08-05T14:51:15+00:00",
      "cve": "CVE-2026-45894",
      "id": "CVE-2026-45894",
      "initial_release_date": "2026-05-27T00:00:00+00:00",
      "product_status:known_affected": "232",
      "product_status:known_not_affected": "42",
      "source": "Red Hat CSAF VEX",
      "status": "final",
      "title": "kernel: iommu/vt-d: Clear Present bit before tearing down PASID entry",
      "url": "https://security.access.redhat.com/data/csaf/v2/vex/2026/cve-2026-45894.json",
      "version": "3"
    },
    "suse_vex": {
      "aggregate_severity": "moderate",
      "current_release_date": "2026-08-06T01:19:06Z",
      "cve": "CVE-2026-45894",
      "id": "CVE-2026-45894",
      "initial_release_date": "2026-05-28T03:56:42Z",
      "product_status:first_fixed": "2",
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      "product_status:known_not_affected": "67",
      "product_status:recommended": "294",
      "source": "SUSE CSAF VEX",
      "status": "interim",
      "title": "SUSE CVE CVE-2026-45894",
      "url": "https://ftp.suse.com/pub/projects/security/csaf-vex/cve-2026-45894.json",
      "version": "14"
    }
  }
}



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Forecast uses a logistic model when the trend is rising, or an exponential decay model when the trend is falling. Fitted via linearized least squares.

Sightings

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Nomenclature

  • Seen: The vulnerability was mentioned, discussed, or observed by the user.
  • Confirmed: The vulnerability has been validated from an analyst's perspective.
  • Published Proof of Concept: A public proof of concept is available for this vulnerability.
  • Exploited: The vulnerability was observed as exploited by the user who reported the sighting.
  • Patched: The vulnerability was observed as successfully patched by the user who reported the sighting.
  • Not exploited: The vulnerability was not observed as exploited by the user who reported the sighting.
  • Not confirmed: The user expressed doubt about the validity of the vulnerability.
  • Not patched: The vulnerability was not observed as successfully patched by the user who reported the sighting.


Detection rules are retrieved from Rulezet.