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CVE-2026-53051 (GCVE-0-2026-53051)

Vulnerability from cvelistv5 – Published: 2026-06-24 16:29 – Updated: 2026-06-24 16:29
VLAI
Title
PCI: tegra194: Fix CBB timeout caused by DBI access before core power-on
Summary
In the Linux kernel, the following vulnerability has been resolved: PCI: tegra194: Fix CBB timeout caused by DBI access before core power-on When PERST# is deasserted twice (assert -> deassert -> assert -> deassert), a CBB (Control Backbone) timeout occurs at DBI register offset 0x8bc (PCIE_MISC_CONTROL_1_OFF). This happens because pci_epc_deinit_notify() and dw_pcie_ep_cleanup() are called before reset_control_deassert() powers on the controller core. The call chain that causes the timeout: pex_ep_event_pex_rst_deassert() pci_epc_deinit_notify() pci_epf_test_epc_deinit() pci_epf_test_clear_bar() pci_epc_clear_bar() dw_pcie_ep_clear_bar() __dw_pcie_ep_reset_bar() dw_pcie_dbi_ro_wr_en() <- Accesses 0x8bc DBI register reset_control_deassert(pcie->core_rst) <- Core powered on HERE The DBI registers, including PCIE_MISC_CONTROL_1_OFF (0x8bc), are only accessible after the controller core is powered on via reset_control_deassert(pcie->core_rst). Accessing them before this point results in a CBB timeout because the hardware is not yet operational. Fix this by moving pci_epc_deinit_notify() and dw_pcie_ep_cleanup() to after reset_control_deassert(pcie->core_rst), ensuring the controller is fully powered on before any DBI register accesses occur.
Severity
5.5 (Medium)
CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:N/I:N/A:H
Assigner
References
Impacted products
Vendor Product Version CPE status
Linux Linux Affected: 72034050ccf4202cd6558b0afd2474f756ea3b9b , < 010983063a806720b45778d191335f8ea864fea3 (git)
Affected: 40e2125381dc11379112485e3eefdd25c6df5375 , < b059a41bdd5b202b2b9d7708403fb43c69689e53 (git)
Affected: 40e2125381dc11379112485e3eefdd25c6df5375 , < ce899f9c019591b73ef84b9afa332ed53beece25 (git)
Affected: 40e2125381dc11379112485e3eefdd25c6df5375 , < 34b3eef48d980cd37b876e128bbf314f69fb5d70 (git)
Affected: 70212c2300971506e986d95000d2745529cac9d7 (git)
Affected: 6.12.2 , < 6.12.91 (semver)
Affected: 6.11.11 , < 6.12 (semver)
guessed Create a notification for this product.
Linux Linux Affected: 6.13
Unaffected: 0 , < 6.13 (semver)
Unaffected: 6.12.91 , ≤ 6.12.* (semver)
Unaffected: 6.18.33 , ≤ 6.18.* (semver)
Unaffected: 7.0.10 , ≤ 7.0.* (semver)
Unaffected: 7.1 , ≤ * (original_commit_for_fix)
guessed Create a notification for this product.
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          "value": "In the Linux kernel, the following vulnerability has been resolved:\n\nPCI: tegra194: Fix CBB timeout caused by DBI access before core power-on\n\nWhen PERST# is deasserted twice (assert -\u003e deassert -\u003e assert -\u003e deassert),\na CBB (Control Backbone) timeout occurs at DBI register offset 0x8bc\n(PCIE_MISC_CONTROL_1_OFF). This happens because pci_epc_deinit_notify()\nand dw_pcie_ep_cleanup() are called before reset_control_deassert() powers\non the controller core.\n\nThe call chain that causes the timeout:\n\n  pex_ep_event_pex_rst_deassert()\n    pci_epc_deinit_notify()\n      pci_epf_test_epc_deinit()\n        pci_epf_test_clear_bar()\n          pci_epc_clear_bar()\n            dw_pcie_ep_clear_bar()\n              __dw_pcie_ep_reset_bar()\n                dw_pcie_dbi_ro_wr_en()      \u003c- Accesses 0x8bc DBI register\n    reset_control_deassert(pcie-\u003ecore_rst)  \u003c- Core powered on HERE\n\nThe DBI registers, including PCIE_MISC_CONTROL_1_OFF (0x8bc), are only\naccessible after the controller core is powered on via\nreset_control_deassert(pcie-\u003ecore_rst). Accessing them before this point\nresults in a CBB timeout because the hardware is not yet operational.\n\nFix this by moving pci_epc_deinit_notify() and dw_pcie_ep_cleanup() to\nafter reset_control_deassert(pcie-\u003ecore_rst), ensuring the controller is\nfully powered on before any DBI register accesses occur."
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      "cve": "CVE-2026-53051",
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      "title": "SUSE CVE CVE-2026-53051",
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}



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