CVE-2026-74439 (GCVE-0-2026-74439)

Vulnerability from cvelistv5 – Published: 2026-08-15 05:59 – Updated: 2026-08-17 05:47
VLAI
Title
iommu/vt-d: Clear Present bit before tearing down scalable-mode context entry
Summary
In the Linux kernel, the following vulnerability has been resolved: iommu/vt-d: Clear Present bit before tearing down scalable-mode context entry device_pasid_table_teardown() zeroes the 128-bit scalable-mode context entry with context_clear_entry() while the Present bit is still set. This creates a window where the hardware can fetch a torn entry, with some fields already zeroed while Present is still set, leading to unpredictable behavior or spurious faults. The context-cache invalidation is issued only after the entry has been zeroed, and intel_pasid_free_table() then frees the PASID directory pages, so the IOMMU can keep walking a stale Present=1 entry that points at freed memory. While x86 provides strong write ordering, the compiler may reorder the two 64-bit writes to the entry, and the hardware fetch is not guaranteed to be atomic with respect to multiple CPU writes. Commit c1e4f1dccbe9d ("iommu/vt-d: Clear Present bit before tearing down context entry") fixed this exact pattern in domain_context_clear_one() and the copied-context path, but device_pasid_table_teardown() was not converted. Align it with the "Guidance to Software for Invalidations" in the VT-d spec, Section 6.5.3.3, using the same ownership handshake as the sibling fix: clear only the Present bit, flush it to the IOMMU, perform the context-cache invalidation, and only then zero the rest of the entry.
Severity
9.3 (Critical)
CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:C/C:H/I:H/A:H
Assigner
References
Impacted products
Vendor Product Version CPE status
Linux Linux Affected: 81e921fd321614c2ad8ac333b041aae1da7a1c6d , < e9e83bcfe37dc719182500dd823c03ab57d934f0 (git)
Affected: 81e921fd321614c2ad8ac333b041aae1da7a1c6d , < 588718101e8449605f1c7e858fecb7cfa701cdab (git)
Affected: 81e921fd321614c2ad8ac333b041aae1da7a1c6d , < 7fd4077dc92b91b1b844333c0a06bb9e286db10a (git)
Affected: 81e921fd321614c2ad8ac333b041aae1da7a1c6d , < f46452c3df7a8d8a5addc0926e76ef19ea7da0a0 (git)
Affected: 333fe86968482ca701c609af590003bcea450e8f (git)
Affected: 6.8.2 , < 6.9 (semver)
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Linux Linux Affected: 6.9
Unaffected: 0 , < 6.9 (semver)
Unaffected: 6.12.97 , ≤ 6.12.* (semver)
Unaffected: 6.18.40 , ≤ 6.18.* (semver)
Unaffected: 7.1.5 , ≤ 7.1.* (semver)
Unaffected: 7.2 , ≤ * (original_commit_for_fix)
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{
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        {
          "defaultStatus": "unaffected",
          "product": "Linux",
          "programFiles": [
            "drivers/iommu/intel/pasid.c"
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          "value": "In the Linux kernel, the following vulnerability has been resolved:\n\niommu/vt-d: Clear Present bit before tearing down scalable-mode context entry\n\ndevice_pasid_table_teardown() zeroes the 128-bit scalable-mode context\nentry with context_clear_entry() while the Present bit is still set. This\ncreates a window where the hardware can fetch a torn entry, with some\nfields already zeroed while Present is still set, leading to unpredictable\nbehavior or spurious faults. The context-cache invalidation is issued only\nafter the entry has been zeroed, and intel_pasid_free_table() then frees\nthe PASID directory pages, so the IOMMU can keep walking a stale Present=1\nentry that points at freed memory.\n\nWhile x86 provides strong write ordering, the compiler may reorder the two\n64-bit writes to the entry, and the hardware fetch is not guaranteed to be\natomic with respect to multiple CPU writes.\n\nCommit c1e4f1dccbe9d (\"iommu/vt-d: Clear Present bit before tearing down\ncontext entry\") fixed this exact pattern in domain_context_clear_one() and\nthe copied-context path, but device_pasid_table_teardown() was not\nconverted.\n\nAlign it with the \"Guidance to Software for Invalidations\" in the VT-d\nspec, Section 6.5.3.3, using the same ownership handshake as the sibling\nfix: clear only the Present bit, flush it to the IOMMU, perform the\ncontext-cache invalidation, and only then zero the rest of the entry."
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            "version": "3.1"
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              "lang": "en",
              "value": "AV:L - The flaw is in Intel VT-d scalable-mode PASID context teardown reached only via local kernel IOMMU device-release paths (intel_iommu_release_device \u2192 device_pasid_table_teardown), triggered by PCI hot-unplug, sysfs driver unbind, or iommu deinit\u2014not by any network-facing protocol.\nAC:L - This is a use-after-free where intel_pasid_free_table() frees PASID directory pages while the IOMMU may still cache a Present=1 context entry; an attacker controlling a PASID-capable device can keep DMA active and time bus removal/teardown to hit the stale-entry window reliably (AC:L per UAF guidance).\nPR:N - A malicious PASID-capable PCIe device can trigger the vulnerable intel_iommu_release_device teardown by physical hot-unplug (pci_stop_and_remove_bus_device) while sustaining DMA, requiring no authenticated host account or capability on the target system.\nUI:N - No victim interaction is required beyond the attacker\u0027s own device removal or driver-unbind orchestration; the vulnerable teardown executes automatically once the PCI/IOMMU release path runs.\nS:C - A stale or torn scalable-mode context entry breaks VT-d DMA isolation\u2014the IOMMU can translate device DMA against freed PASID table memory, crossing the device/host (or guest/host) IOMMU security boundary per kernel IOMMU bypass guidance.\nC:H - With the IOMMU walking freed PASID directory pages, a controlled device can DMA-read host physical memory outside its assigned domain, yielding arbitrary cross-boundary read disclosure (C:H; UAF enables attacker influence over translation contents).\nI:H - The same mistranslation gives the device an arbitrary DMA write primitive against host memory outside its domain, enabling data modification and potential control-flow hijack via memory corruption (standard UAF/IOMMU-bypass I:H guidance).\nA:H - The commit documents unpredictable behavior and spurious DMAR faults from torn Present entries; freed PASID tables under active IOMMU walks can fault-storm, hang, or panic the host\u2014any kernel crash/UAF qualifies as A:H."
            }
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      "providerMetadata": {
        "dateUpdated": "2026-08-17T05:47:13.219Z",
        "orgId": "416baaa9-dc9f-4396-8d5f-8c081fb06d67",
        "shortName": "Linux"
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    "assignerShortName": "Linux",
    "cveId": "CVE-2026-74439",
    "datePublished": "2026-08-15T05:59:36.655Z",
    "dateReserved": "2026-08-15T05:44:03.897Z",
    "dateUpdated": "2026-08-17T05:47:13.219Z",
    "state": "PUBLISHED"
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      "date": "2026-08-18",
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  }
}



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Forecast uses a logistic model when the trend is rising, or an exponential decay model when the trend is falling. Fitted via linearized least squares.

Sightings

Author Source Type Date Other

Nomenclature

  • Seen: The vulnerability was mentioned, discussed, or observed by the user.
  • Confirmed: The vulnerability has been validated from an analyst's perspective.
  • Published Proof of Concept: A public proof of concept is available for this vulnerability.
  • Exploited: The vulnerability was observed as exploited by the user who reported the sighting.
  • Patched: The vulnerability was observed as successfully patched by the user who reported the sighting.
  • Not exploited: The vulnerability was not observed as exploited by the user who reported the sighting.
  • Not confirmed: The user expressed doubt about the validity of the vulnerability.
  • Not patched: The vulnerability was not observed as successfully patched by the user who reported the sighting.


Detection rules are retrieved from Rulezet.